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Searched refs:SCG_CSR_SCS_MASK (Results 1 – 5 of 5) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
Dsystem_RV32M1_zero_riscy.c397 switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) { in SystemCoreClockUpdate()
Dsystem_RV32M1_ri5cy.c394 switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) { in SystemCoreClockUpdate()
DRV32M1_ri5cy.h16337 #define SCG_CSR_SCS_MASK (0xF000000U) macro
16349 …) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_SCS_SHIFT)) & SCG_CSR_SCS_MASK)
DRV32M1_zero_riscy.h17165 #define SCG_CSR_SCS_MASK (0xF000000U) macro
17177 …) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_SCS_SHIFT)) & SCG_CSR_SCS_MASK)
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_clock.c29 #define SCG_CSR_SCS_VAL ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT)