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Searched refs:SCG_CSR_DIVCORE_SHIFT (Results 1 – 4 of 4) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
Dsystem_RV32M1_zero_riscy.c395 Divider = ((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1; in SystemCoreClockUpdate()
Dsystem_RV32M1_ri5cy.c392 Divider = ((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1; in SystemCoreClockUpdate()
DRV32M1_ri5cy.h16317 #define SCG_CSR_DIVCORE_SHIFT (16U) macro
16336 …_DIVCORE(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVCORE_SHIFT)) & SCG_CS…
DRV32M1_zero_riscy.h17145 #define SCG_CSR_DIVCORE_SHIFT (16U) macro
17164 …_DIVCORE(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVCORE_SHIFT)) & SCG_CS…