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Searched refs:HWCFG0 (Results 1 – 3 of 3) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_xrdc.c116 … config->masterNumber = ((base->HWCFG0 & XRDC_HWCFG0_NMSTR_MASK) >> XRDC_HWCFG0_NMSTR_SHIFT) + 1U; in XRDC_GetHardwareConfig()
117 config->domainNumber = ((base->HWCFG0 & XRDC_HWCFG0_NDID_MASK) >> XRDC_HWCFG0_NDID_SHIFT) + 1U; in XRDC_GetHardwareConfig()
118 config->pacNumber = ((base->HWCFG0 & XRDC_HWCFG0_NPAC_MASK) >> XRDC_HWCFG0_NPAC_SHIFT) + 1U; in XRDC_GetHardwareConfig()
119 config->mrcNumber = ((base->HWCFG0 & XRDC_HWCFG0_NMRC_MASK) >> XRDC_HWCFG0_NMRC_SHIFT) + 1U; in XRDC_GetHardwareConfig()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h23257 …__I uint32_t HWCFG0; /**< Hardware Configuration Register 0, offset: 0… member
DRV32M1_zero_riscy.h30789 …__I uint32_t HWCFG0; /**< Hardware Configuration Register 0, offset: 0… member