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Searched refs:CHANNEL (Results 1 – 8 of 8) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_intmux.h81 base->CHANNEL[channel].CHn_CSR |= INTMUX_CHn_CSR_RST_MASK; in INTMUX_ResetChannel()
101 base->CHANNEL[channel].CHn_CSR = INTMUX_CHn_CSR_AND(logic); in INTMUX_SetChannelMode()
120 …base->CHANNEL[channel].CHn_IER_31_0 |= (1U << ((uint32_t)irq - FSL_FEATURE_INTMUX_IRQ_START_INDEX)… in INTMUX_EnableInterrupt()
135 …base->CHANNEL[channel].CHn_IER_31_0 &= ~(1U << ((uint32_t)irq - FSL_FEATURE_INTMUX_IRQ_START_INDEX… in INTMUX_DisableInterrupt()
153 return base->CHANNEL[channel].CHn_IPR_31_0; in INTMUX_GetChannelPendingSources()
Dfsl_lpit.h299 base->CHANNEL[channel].TVAL = ticks; in LPIT_SetTimerPeriod()
317 return base->CHANNEL[channel].CVAL; in LPIT_GetCurrentTimerCount()
Dfsl_lpit.c131 base->CHANNEL[channel].TCTRL = reg; in LPIT_SetupChannel()
Dfsl_intmux.c85 pendingIrqOffset = intmuxBase->CHANNEL[channel].CHn_VEC; in INTMUX_CommonIRQHandler()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
Dsystem_RV32M1_zero_riscy.c480 SYSTICK_LPIT->CHANNEL[SYSTICK_LPIT_CH].TVAL = (CLOCK_GetIpFreq(kCLOCK_Lpit1) / tickRateHz) - 1;
Dsystem_RV32M1_ri5cy.c477 SYSTICK_LPIT->CHANNEL[SYSTICK_LPIT_CH].TVAL = (CLOCK_GetIpFreq(kCLOCK_Lpit0) / tickRateHz) - 1;
DRV32M1_ri5cy.h8148 } CHANNEL[8]; member
11210 } CHANNEL[4]; member
DRV32M1_zero_riscy.h8292 } CHANNEL[8]; member
11354 } CHANNEL[4]; member