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Searched refs:RISCV32 (Results 1 – 14 of 14) sorted by relevance

/Zephyr-latest/boards/renode/riscv32_virtual/support/
Driscv32_virtual.resc1 :name: RISCV32-Virtual
2 :description: This script is prepared to run Zephyr on a Renode RISCV32 board.
4 $name?="RISCV32-Virtual"
/Zephyr-latest/soc/renode/riscv_virtual/
DKconfig.soc7 Renode RISCV32 Virtual system implementation
/Zephyr-latest/boards/renode/riscv32_virtual/
Driscv32_virtual.dts12 model = "Renode RISCV32 Virtual target";
/Zephyr-latest/boards/qemu/riscv32/doc/
Dindex.rst6 The RISCV32 QEMU board configuration is used to emulate the RISCV32 architecture.
/Zephyr-latest/boards/qemu/riscv32_xip/doc/
Dindex.rst6 The RISCV32 XIP QEMU board configuration is used to emulate the RISCV32 architecture.
/Zephyr-latest/boards/renode/riscv32_virtual/doc/
Dindex.rst6 The RISCV32 Virtual board is a virtual platform made with Renode as an alternative to QEMU.
/Zephyr-latest/boards/qemu/riscv32e/doc/
Dindex.rst6 The RISCV32E QEMU board configuration is used to emulate the RISCV32 (RV32E) architecture.
/Zephyr-latest/soc/andestech/ae350/
DKconfig29 bool "RISCV32 CPU ISA"
/Zephyr-latest/subsys/logging/
DKconfig.misc35 RISCV32) and execution time also up to 40%.
/Zephyr-latest/doc/releases/
Drelease-notes-1.13.rst682 * :github:`3826` - RISCV32 {__irq_wrapper} exception handling error under compressed instruction mo…
Drelease-notes-2.0.rst1486 * :github:`3651` - add tickless idle and kernel support to RISCV32 pulpino
Drelease-notes-2.5.rst1905 * :github:`17743` - cross compiling for RISCV32 fails as compiler flags are not supplied by board b…
Drelease-notes-3.1.rst1987 * :github:`17743` - cross compiling for RISCV32 fails as compiler flags are not supplied by board b…
Drelease-notes-2.6.rst1452 * :github:`34026` - RISCV32 QEMU illegal instruction exception / floating point support