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/hal_nxp-latest/mcux/mcux-sdk/components/wifi_bt_module/Murata/tx_pwr_limits/
Dwlan_txpwrlimit_cfg_murata_2EL_WW.h2795 ….rupwrlimit_config[0] = {.start_freq = 2407, .width = 20, .chan_num = 1, .ruPower = {-1, 2, 5, 8, …
2797 ….rupwrlimit_config[1] = {.start_freq = 2407, .width = 20, .chan_num = 2, .ruPower = {-1, 2, 5, 8, …
2799 ….rupwrlimit_config[2] = {.start_freq = 2407, .width = 20, .chan_num = 3, .ruPower = {-1, 2, 5, 8, …
2801 ….rupwrlimit_config[3] = {.start_freq = 2407, .width = 20, .chan_num = 4, .ruPower = {-1, 2, 5, 8, …
2803 ….rupwrlimit_config[4] = {.start_freq = 2407, .width = 20, .chan_num = 5, .ruPower = {-1, 2, 5, 8, …
2805 ….rupwrlimit_config[5] = {.start_freq = 2407, .width = 20, .chan_num = 6, .ruPower = {-1, 2, 5, 8, …
2807 ….rupwrlimit_config[6] = {.start_freq = 2407, .width = 20, .chan_num = 7, .ruPower = {-1, 2, 5, 8, …
2809 ….rupwrlimit_config[7] = {.start_freq = 2407, .width = 20, .chan_num = 8, .ruPower = {-1, 2, 5, 8, …
2811 ….rupwrlimit_config[8] = {.start_freq = 2407, .width = 20, .chan_num = 9, .ruPower = {-1, 2, 5, 8, …
2813 ….rupwrlimit_config[9] = {.start_freq = 2407, .width = 20, .chan_num = 10, .ruPower = {-1, 2, 5, 8,…
[all …]
Dwlan_txpwrlimit_cfg_murata_2EL_CA_RU_Tx_power.h2951 ….rupwrlimit_config[0] = {.start_freq = 2407, .width = 20, .chan_num = 1, .ruPower = {11, 11, 11, 1…
2953 ….rupwrlimit_config[1] = {.start_freq = 2407, .width = 20, .chan_num = 2, .ruPower = {12, 12, 12, 1…
2955 ….rupwrlimit_config[2] = {.start_freq = 2407, .width = 20, .chan_num = 3, .ruPower = {12, 12, 12, 1…
2957 ….rupwrlimit_config[3] = {.start_freq = 2407, .width = 20, .chan_num = 4, .ruPower = {12, 12, 12, 1…
2959 ….rupwrlimit_config[4] = {.start_freq = 2407, .width = 20, .chan_num = 5, .ruPower = {12, 12, 12, 1…
2961 ….rupwrlimit_config[5] = {.start_freq = 2407, .width = 20, .chan_num = 6, .ruPower = {12, 12, 12, 1…
2963 ….rupwrlimit_config[6] = {.start_freq = 2407, .width = 20, .chan_num = 7, .ruPower = {12, 12, 12, 1…
2965 ….rupwrlimit_config[7] = {.start_freq = 2407, .width = 20, .chan_num = 8, .ruPower = {12, 12, 12, 1…
2967 ….rupwrlimit_config[8] = {.start_freq = 2407, .width = 20, .chan_num = 9, .ruPower = {12, 12, 12, 1…
2969 ….rupwrlimit_config[9] = {.start_freq = 2407, .width = 20, .chan_num = 10, .ruPower = {12, 12, 12, …
[all …]
Dwlan_txpwrlimit_cfg_murata_2EL_US_RU_Tx_power.h2975 ….rupwrlimit_config[0] = {.start_freq = 2407, .width = 20, .chan_num = 1, .ruPower = {11, 11, 11, 1…
2977 ….rupwrlimit_config[1] = {.start_freq = 2407, .width = 20, .chan_num = 2, .ruPower = {12, 12, 12, 1…
2979 ….rupwrlimit_config[2] = {.start_freq = 2407, .width = 20, .chan_num = 3, .ruPower = {12, 12, 12, 1…
2981 ….rupwrlimit_config[3] = {.start_freq = 2407, .width = 20, .chan_num = 4, .ruPower = {12, 12, 12, 1…
2983 ….rupwrlimit_config[4] = {.start_freq = 2407, .width = 20, .chan_num = 5, .ruPower = {12, 12, 12, 1…
2985 ….rupwrlimit_config[5] = {.start_freq = 2407, .width = 20, .chan_num = 6, .ruPower = {12, 12, 12, 1…
2987 ….rupwrlimit_config[6] = {.start_freq = 2407, .width = 20, .chan_num = 7, .ruPower = {12, 12, 12, 1…
2989 ….rupwrlimit_config[7] = {.start_freq = 2407, .width = 20, .chan_num = 8, .ruPower = {12, 12, 12, 1…
2991 ….rupwrlimit_config[8] = {.start_freq = 2407, .width = 20, .chan_num = 9, .ruPower = {12, 12, 12, 1…
2993 ….rupwrlimit_config[9] = {.start_freq = 2407, .width = 20, .chan_num = 10, .ruPower = {12, 12, 12, …
[all …]
Dwlan_txpwrlimit_cfg_murata_2EL_JP_RU_Tx_power.h2939 ….rupwrlimit_config[0] = {.start_freq = 2407, .width = 20, .chan_num = 1, .ruPower = {9, 10, 13, 15…
2941 ….rupwrlimit_config[1] = {.start_freq = 2407, .width = 20, .chan_num = 2, .ruPower = {9, 10, 13, 15…
2943 ….rupwrlimit_config[2] = {.start_freq = 2407, .width = 20, .chan_num = 3, .ruPower = {9, 10, 13, 15…
2945 ….rupwrlimit_config[3] = {.start_freq = 2407, .width = 20, .chan_num = 4, .ruPower = {9, 10, 13, 15…
2947 ….rupwrlimit_config[4] = {.start_freq = 2407, .width = 20, .chan_num = 5, .ruPower = {9, 10, 13, 15…
2949 ….rupwrlimit_config[5] = {.start_freq = 2407, .width = 20, .chan_num = 6, .ruPower = {9, 10, 13, 15…
2951 ….rupwrlimit_config[6] = {.start_freq = 2407, .width = 20, .chan_num = 7, .ruPower = {9, 10, 13, 15…
2953 ….rupwrlimit_config[7] = {.start_freq = 2407, .width = 20, .chan_num = 8, .ruPower = {9, 10, 13, 15…
2955 ….rupwrlimit_config[8] = {.start_freq = 2407, .width = 20, .chan_num = 9, .ruPower = {9, 10, 13, 15…
2957 ….rupwrlimit_config[9] = {.start_freq = 2407, .width = 20, .chan_num = 10, .ruPower = {9, 10, 13, 1…
[all …]
Dwlan_txpwrlimit_cfg_murata_2EL_EU_RU_Tx_power.h2927 ….rupwrlimit_config[0] = {.start_freq = 2407, .width = 20, .chan_num = 1, .ruPower = {7, 9, 12, 14,…
2929 ….rupwrlimit_config[1] = {.start_freq = 2407, .width = 20, .chan_num = 2, .ruPower = {7, 9, 12, 14,…
2931 ….rupwrlimit_config[2] = {.start_freq = 2407, .width = 20, .chan_num = 3, .ruPower = {7, 9, 12, 14,…
2933 ….rupwrlimit_config[3] = {.start_freq = 2407, .width = 20, .chan_num = 4, .ruPower = {7, 9, 12, 14,…
2935 ….rupwrlimit_config[4] = {.start_freq = 2407, .width = 20, .chan_num = 5, .ruPower = {7, 9, 12, 14,…
2937 ….rupwrlimit_config[5] = {.start_freq = 2407, .width = 20, .chan_num = 6, .ruPower = {7, 9, 12, 14,…
2939 ….rupwrlimit_config[6] = {.start_freq = 2407, .width = 20, .chan_num = 7, .ruPower = {7, 9, 12, 14,…
2941 ….rupwrlimit_config[7] = {.start_freq = 2407, .width = 20, .chan_num = 8, .ruPower = {7, 9, 12, 14,…
2943 ….rupwrlimit_config[8] = {.start_freq = 2407, .width = 20, .chan_num = 9, .ruPower = {7, 9, 12, 14,…
2945 ….rupwrlimit_config[9] = {.start_freq = 2407, .width = 20, .chan_num = 10, .ruPower = {7, 9, 12, 14…
[all …]
/hal_nxp-latest/mcux/mcux-sdk/components/wifi_bt_module/u-blox/tx_pwr_limits/
Dwlan_txpwrlimit_cfg_jody_w5_WW.h2795 ….rupwrlimit_config[0] = {.start_freq = 2407, .width = 20, .chan_num = 1, .ruPower = {-1, 2, 5, 8, …
2797 ….rupwrlimit_config[1] = {.start_freq = 2407, .width = 20, .chan_num = 2, .ruPower = {-1, 2, 5, 8, …
2799 ….rupwrlimit_config[2] = {.start_freq = 2407, .width = 20, .chan_num = 3, .ruPower = {-1, 2, 5, 8, …
2801 ….rupwrlimit_config[3] = {.start_freq = 2407, .width = 20, .chan_num = 4, .ruPower = {-1, 2, 5, 8, …
2803 ….rupwrlimit_config[4] = {.start_freq = 2407, .width = 20, .chan_num = 5, .ruPower = {-1, 2, 5, 8, …
2805 ….rupwrlimit_config[5] = {.start_freq = 2407, .width = 20, .chan_num = 6, .ruPower = {-1, 2, 5, 8, …
2807 ….rupwrlimit_config[6] = {.start_freq = 2407, .width = 20, .chan_num = 7, .ruPower = {-1, 2, 5, 8, …
2809 ….rupwrlimit_config[7] = {.start_freq = 2407, .width = 20, .chan_num = 8, .ruPower = {-1, 2, 5, 8, …
2811 ….rupwrlimit_config[8] = {.start_freq = 2407, .width = 20, .chan_num = 9, .ruPower = {-1, 2, 5, 8, …
2813 ….rupwrlimit_config[9] = {.start_freq = 2407, .width = 20, .chan_num = 10, .ruPower = {-1, 2, 5, 8,…
[all …]
/hal_nxp-latest/mcux/mcux-sdk/components/wifi_bt_module/AzureWave/tx_pwr_limits/
Dwlan_txpwrlimit_cfg_WW_rw610.h3325 ….rupwrlimit_config[0] = {.start_freq = 2407, .width = 20, .chan_num = 1, .ruPower = {-1, 2, 5, 8, …
3327 ….rupwrlimit_config[1] = {.start_freq = 2407, .width = 20, .chan_num = 2, .ruPower = {-1, 2, 5, 8, …
3329 ….rupwrlimit_config[2] = {.start_freq = 2407, .width = 20, .chan_num = 3, .ruPower = {-1, 2, 5, 8, …
3331 ….rupwrlimit_config[3] = {.start_freq = 2407, .width = 20, .chan_num = 4, .ruPower = {-1, 2, 5, 8, …
3333 ….rupwrlimit_config[4] = {.start_freq = 2407, .width = 20, .chan_num = 5, .ruPower = {-1, 2, 5, 8, …
3335 ….rupwrlimit_config[5] = {.start_freq = 2407, .width = 20, .chan_num = 6, .ruPower = {-1, 2, 5, 8, …
3337 ….rupwrlimit_config[6] = {.start_freq = 2407, .width = 20, .chan_num = 7, .ruPower = {-1, 2, 5, 8, …
3339 ….rupwrlimit_config[7] = {.start_freq = 2407, .width = 20, .chan_num = 8, .ruPower = {-1, 2, 5, 8, …
3341 ….rupwrlimit_config[8] = {.start_freq = 2407, .width = 20, .chan_num = 9, .ruPower = {-1, 2, 5, 8, …
3343 ….rupwrlimit_config[9] = {.start_freq = 2407, .width = 20, .chan_num = 10, .ruPower = {-1, 2, 5, 8,…
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW40Z4/drivers/
Dfsl_bitaccess.h79 #define BME_BFI8(addr, wdata, bit, width) (*(volatile uint8_t*)((uintptr_t)addr | BME_BFI_MASK(bit,… argument
80 #define BME_BFI16(addr, wdata, bit, width) (*(volatile uint16_t*)((uintptr_t)addr | BME_BFI_MASK(bi… argument
81 #define BME_BFI32(addr, wdata, bit, width) (*(volatile uint32_t*)((uintptr_t)addr | BME_BFI_MASK(bi… argument
84 #define BME_UBFX8(addr, bit, width) (*(volatile uint8_t*)((uintptr_t)addr | BME_UBFX_MASK(bit,width… argument
85 #define BME_UBFX16(addr, bit, width) (*(volatile uint16_t*)((uintptr_t)addr | BME_UBFX_MASK(bit,wid… argument
86 #define BME_UBFX32(addr, bit, width) (*(volatile uint32_t*)((uintptr_t)addr | BME_UBFX_MASK(bit,wid… argument
/hal_nxp-latest/mcux/mcux-sdk/drivers/lpc_dma/
Dfsl_dma.c290 uint32_t width = 0, srcInc = 0, dstInc = 0, transferCount = 0; in DMA_SetupDescriptor() local
292 width = (xfercfg & DMA_CHANNEL_XFERCFG_WIDTH_MASK) >> DMA_CHANNEL_XFERCFG_WIDTH_SHIFT; in DMA_SetupDescriptor()
298 if (width == 2U) in DMA_SetupDescriptor()
300 width = kDMA_Transfer32BitWidth; in DMA_SetupDescriptor()
304 width += 1U; in DMA_SetupDescriptor()
312 if (((NULL != srcStartAddr) && (0UL == ((uint32_t)(uint32_t *)srcStartAddr) % width)) && in DMA_SetupDescriptor()
313 ((NULL != dstStartAddr) && (0UL == ((uint32_t)(uint32_t *)dstStartAddr) % width))) in DMA_SetupDescriptor()
326 …dAddr = DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)srcStartAddr, srcInc, transferCount * width, width); in DMA_SetupDescriptor()
327 …dAddr = DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)dstStartAddr, dstInc, transferCount * width, width); in DMA_SetupDescriptor()
366 uint32_t width = 0, srcInc = 0, dstInc = 0, transferCount = 0; in DMA_SetupChannelDescriptor() local
[all …]
Dfsl_dma.h77 #define DMA_ALLOCATE_DATA_TRANSFER_BUFFER(name, width) SDK_ALIGN(name, width) argument
96 #define DMA_DESCRIPTOR_END_ADDRESS(start, inc, bytes, width) \ argument
97 ((uint32_t *)((uint32_t)(start) + (inc) * (bytes) - (inc) * (width)))
99 #define DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes) \ argument
100 (DMA_SetChannelXferConfig(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes))
487 …bool reload, bool clrTrig, bool intA, bool intB, uint8_t width, uint8_t srcInc, uint8_t dstInc, ui… in DMA_SetChannelXferConfig() argument
489 assert(((uint32_t)bytes / (uint32_t)width) <= DMA_MAX_TRANSFER_COUNT); in DMA_SetChannelXferConfig()
493 DMA_CHANNEL_XFERCFG_WIDTH((uint32_t)width == 4UL ? 2UL : ((uint32_t)width - 1UL)) | in DMA_SetChannelXferConfig()
496 DMA_CHANNEL_XFERCFG_XFERCOUNT((uint32_t)bytes / (uint32_t)width - 1UL)); in DMA_SetChannelXferConfig()
/hal_nxp-latest/mcux/mcux-sdk/drivers/i3c/
Dfsl_i3c.h987 static inline void I3C_MasterEnableDMA(I3C_Type *base, bool enableTx, bool enableRx, uint32_t width) in I3C_MasterEnableDMA() argument
989 assert(width <= 2U); in I3C_MasterEnableDMA()
991 …_DMAFB(enableRx ? 2U : 0U) | I3C_MDMACTRL_DMATB(enableTx ? 2U : 0U) | I3C_MDMACTRL_DMAWIDTH(width); in I3C_MasterEnableDMA()
1001 static inline uint32_t I3C_MasterGetTxFifoAddress(I3C_Type *base, uint32_t width) in I3C_MasterGetTxFifoAddress() argument
1003 assert(width <= 2U); in I3C_MasterGetTxFifoAddress()
1004 return (uint32_t)((width == 2U) ? &base->MWDATAH : &base->MWDATAB); in I3C_MasterGetTxFifoAddress()
1014 static inline uint32_t I3C_MasterGetRxFifoAddress(I3C_Type *base, uint32_t width) in I3C_MasterGetRxFifoAddress() argument
1016 assert(width <= 2U); in I3C_MasterGetRxFifoAddress()
1017 return (uint32_t)((width == 2U) ? &base->MRDATAH : &base->MRDATAB); in I3C_MasterGetRxFifoAddress()
1673 static inline void I3C_SlaveEnableDMA(I3C_Type *base, bool enableTx, bool enableRx, uint32_t width) in I3C_SlaveEnableDMA() argument
[all …]
/hal_nxp-latest/mcux/mcux-sdk/drivers/jpegdec/
Dfsl_jpegdec.c216 uint16_t width, height; in JPEGDEC_ParseHeader() local
325 width = JPEG_GET_U16(&imageBuf[5]); in JPEGDEC_ParseHeader()
326 if ((height > 0x2000U) || (width > 0x2000U) || (height < 64U) || (width < 64U)) in JPEGDEC_ParseHeader()
334 config->width = (uint32_t)width; in JPEGDEC_ParseHeader()
338 if (((height & 0xFU) != 0U) || ((width & 0xFU) != 0U)) in JPEGDEC_ParseHeader()
346 if (((height & 0x7U) != 0U) || ((width & 0xFU) != 0U)) in JPEGDEC_ParseHeader()
354 if (((height & 0x7U) != 0U) || ((width & 0x7U) != 0U)) in JPEGDEC_ParseHeader()
400 base->wrapper->IMGSIZE = (uint32_t)config->height | ((uint32_t)config->width << 16U); in JPEGDEC_ConfigDecoder()
450 descriptor->config.width = 0U; in JPEGDEC_DescptReset()
/hal_nxp-latest/mcux/mcux-sdk/components/video/display/dc/elcdif/
Dfsl_dc_fb_elcdif.c81 elcdifConfig.panelWidth = dcConfig->width; in DC_FB_ELCDIF_Init()
95 dcHandle->width = dcConfig->width; in DC_FB_ELCDIF_Init()
172 assert(fbInfo->width == dcHandle->width); in DC_FB_ELCDIF_SetLayerConfig()
174 … assert(fbInfo->strideBytes == VIDEO_GetPixelSizeBits(fbInfo->pixelFormat) * dcHandle->width / 8U); in DC_FB_ELCDIF_SetLayerConfig()
195 fbInfo->width = dcHandle->width; in DC_FB_ELCDIF_GetLayerDefaultConfig()
197 fbInfo->strideBytes = 2U * dcHandle->width; in DC_FB_ELCDIF_GetLayerDefaultConfig()
/hal_nxp-latest/mcux/mcux-sdk/components/video/display/dc/lcdif/
Dfsl_dc_fb_lcdif.c130 lcdifConfig.panelWidth = dcConfig->width; in DC_FB_LCDIF_Init()
142 dcHandle->width = dcConfig->width; in DC_FB_LCDIF_Init()
267 assert(fbInfo->width == dcHandle->width); in DC_FB_LCDIF_SetLayerConfig()
288 dcHandle->layers[layer].fbConfig.width = fbInfo->width; in DC_FB_LCDIF_SetLayerConfig()
321 fbInfo->width = dcHandle->width; in DC_FB_LCDIF_GetLayerDefaultConfig()
323 fbInfo->strideBytes = DC_FB_LCDIF_DEFAULT_BYTE_PER_PIXEL * dcHandle->width; in DC_FB_LCDIF_GetLayerDefaultConfig()
/hal_nxp-latest/mcux/mcux-sdk/components/video/display/dc/lcdifv2/
Dfsl_dc_fb_lcdifv2.c86 lcdifv2Config.panelWidth = dcConfig->width; in DC_FB_LCDIFV2_Init()
98 dcHandle->width = dcConfig->width; in DC_FB_LCDIFV2_Init()
195 LCDIFV2_SetLayerSize(lcdifv2, layer, fbInfo->width, fbInfo->height); in DC_FB_LCDIFV2_SetLayerConfig()
213 fbInfo->width = dcHandle->width; in DC_FB_LCDIFV2_GetLayerDefaultConfig()
215 fbInfo->strideBytes = DC_FB_LCDIFV2_DEFAULT_BYTE_PER_PIXEL * dcHandle->width; in DC_FB_LCDIFV2_GetLayerDefaultConfig()
/hal_nxp-latest/mcux/mcux-sdk/components/video/display/dc/lcdifv3/
Dfsl_dc_fb_lcdifv3.c104 lcdifv3Config.panelWidth = dcConfig->width;
116 dcHandle->width = dcConfig->width;
213 LCDIFV3_SetLayerSize(lcdifv3, fbInfo->width, fbInfo->height);
231 fbInfo->width = dcHandle->width;
233 fbInfo->strideBytes = DC_FB_LCDIFV3_DEFAULT_BYTE_PER_PIXEL * dcHandle->width;
/hal_nxp-latest/mcux/mcux-sdk/drivers/lcdif/
Dfsl_lcdif.c321 …base->FRAMEBUFFERSIZE = LCDIF_FRAMEBUFFERSIZE_WIDTH(config->width) | LCDIF_FRAMEBUFFERSIZE_HEIGHT(… in LCDIF_SetFrameBufferConfig()
344 …LCDIF_Type *base, uint8_t displayIndex, uint16_t topLeftX, uint16_t topLeftY, uint16_t width, uint… in LCDIF_SetFrameBufferPosition() argument
347 … base->FRAMEBUFFERSIZE = LCDIF_FRAMEBUFFERSIZE_WIDTH(width) | LCDIF_FRAMEBUFFERSIZE_HEIGHT(height); in LCDIF_SetFrameBufferPosition()
380 …base->OVERLAYSIZE = LCDIF_OVERLAYSIZE_WIDTH(config->width) | LCDIF_OVERLAYSIZE_HEIGHT(config->… in LCDIF_SetOverlayLayerConfig()
395 …base->OVERLAYSIZE1 = LCDIF_OVERLAYSIZE_WIDTH(config->width) | LCDIF_OVERLAYSIZE_HEIGHT(config-… in LCDIF_SetOverlayLayerConfig()
428 uint16_t width, in LCDIF_SetOverlayLayerPosition() argument
436 base->OVERLAYSIZE = LCDIF_OVERLAYSIZE_WIDTH(width) | LCDIF_OVERLAYSIZE_HEIGHT(height); in LCDIF_SetOverlayLayerPosition()
441 base->OVERLAYSIZE1 = LCDIF_OVERLAYSIZE_WIDTH(width) | LCDIF_OVERLAYSIZE_HEIGHT(height); in LCDIF_SetOverlayLayerPosition()
891 uint16_t width = endX - startX + 1U; in LCDIF_DbiSelectArea() local
896 …e->HDISPLAY0 = LCDIF_HDISPLAY0_DISPLAY_END((uint32_t)width) | LCDIF_HDISPLAY0_TOTAL((uint32_t)widt… in LCDIF_DbiSelectArea()
/hal_nxp-latest/mcux/mcux-sdk/components/video/display/dc/dsi_cmd/
Dfsl_dc_fb_dsi_cmd.c170 fbInfo->width = panelHandle->width; in DC_FB_DSI_CMD_GetLayerDefaultConfig()
172 … fbInfo->strideBytes = panelHandle->width * VIDEO_GetPixelSizeBits(panelHandle->pixelFormat) / 8U; in DC_FB_DSI_CMD_GetLayerDefaultConfig()
189 uint32_t minorLoopBytes = (uint32_t)fbInfo->width * (uint32_t)byteperpixel; in DC_FB_DSI_CMD_SetFrameBuffer()
198 …MIPI_DSI_SelectArea(dsiDevice, fbInfo->startX, fbInfo->startY, fbInfo->startX + fbInfo->width - 1U, in DC_FB_DSI_CMD_SetFrameBuffer()
293 minorLoopBytes = (uint32_t)fbInfo->width * (uint32_t)byteperpixel; in DC_FB_DSI_CMD_TE_IRQHandler()
/hal_nxp-latest/mcux/mcux-sdk/drivers/csi/
Dfsl_csi.c238 imgWidth_Bytes = (uint32_t)config->width * (uint32_t)config->bytesPerPixel; in CSI_Init()
289 … (((uint32_t)config->width * (uint32_t)busCyclePerPixel) << CSI_IMAG_PARA_IMAGE_WIDTH_SHIFT) | in CSI_Init()
413 config->width = 320U; in CSI_GetDefaultConfig()
1069 imgWidth_Bytes = (uint32_t)config->width * CSI_FRAG_INPUT_BYTES_PER_PIXEL; in CSI_FragModeCreateHandle()
1087 handle->width = config->width; in CSI_FragModeCreateHandle()
1089 handle->dmaBytePerLine = config->width * CSI_FRAG_INPUT_BYTES_PER_PIXEL; in CSI_FragModeCreateHandle()
1145 … (uint32_t)config->dmaBufferLine * (uint32_t)config->width * CSI_FRAG_INPUT_BYTES_PER_PIXEL); in CSI_FragModeCreateHandle()
1148 … (uint32_t)config->dmaBufferLine * (uint32_t)config->width * CSI_FRAG_INPUT_BYTES_PER_PIXEL); in CSI_FragModeCreateHandle()
1188 handle->windowLRX = handle->width - 1U; in CSI_FragModeTransferCaptureImage()
1225 … (((uint32_t)handle->width * CSI_FRAG_INPUT_BYTES_PER_PIXEL) << CSI_IMAG_PARA_IMAGE_WIDTH_SHIFT) | in CSI_FragModeTransferCaptureImage()
/hal_nxp-latest/mcux/mcux-sdk/drivers/pxp/
Dfsl_pxp.c152 uint16_t width,
625 …LRC = PXP_OUT_LRC_Y((uint32_t)config->height - 1U) | PXP_OUT_LRC_X((uint32_t)config->width - 1U); in PXP_SetOutputBufferConfig()
632 … base->DITHER_STORE_SIZE_CH0 = PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH((uint32_t)config->width - 1U) | in PXP_SetOutputBufferConfig()
651 uint16_t width, in PXP_BuildRect() argument
688 PXP_SetAlphaSurfacePosition(base, 0, 0, width, height); in PXP_BuildRect()
703 outputBufferConfig.width = width; in PXP_BuildRect()
1198 uint16_t width, in PXP_StartRectCopy() argument
1227 PXP_SetAlphaSurfacePosition(base, 0U, 0U, width - 1U, height - 1U); in PXP_StartRectCopy()
1241 outputBufferConfig.width = width; in PXP_StartRectCopy()
1266 if ((0U == config->height) || (0U == config->width)) in PXP_StartPictureCopy()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/components/video/display/dc/dbi/
Dfsl_dc_fb_dbi.c99 … fbInfo->startX + fbInfo->width - 1U, fbInfo->startY + fbInfo->height - 1U); in DC_FB_DBI_SetLayerConfig()
108 fbInfo->width = dcDbiHandle->width; in DC_FB_DBI_GetLayerDefaultConfig()
110 … fbInfo->strideBytes = dcDbiHandle->width * VIDEO_GetPixelSizeBits(dcDbiHandle->pixelFormat) / 8U; in DC_FB_DBI_GetLayerDefaultConfig()
/hal_nxp-latest/mcux/mcux-sdk/components/video/camera/device/ov7725/
Dfsl_ov7725.c359 uint16_t width, height; in OV7725_Init() local
369 width = FSL_VIDEO_EXTRACT_WIDTH(config->resolution); in OV7725_Init()
372 if ((width > 640U) || (height > 480U)) in OV7725_Init()
445 width += 2U; in OV7725_Init()
494 hsize = width + 16U; in OV7725_Init()
501 OV7725_CHECK_RET(OV7725_WriteReg(handle, OV7725_HOUTSIZE_REG, (uint8_t)(width >> 2U))); in OV7725_Init()
509 …WriteReg(handle, OV7725_EXHCH_REG, (((uint8_t)height & 1U) << 2U) | (((uint8_t)width & 3U) << 0U)); in OV7725_Init()
/hal_nxp-latest/s32/drivers/s32k3/Fls/src/
DQspi_Ip.c282 uint8 width, in Qspi_Ip_SetBitfield() argument
296 mask = ((1UL << (uint32)width) - 1UL) << (uint32)shift; in Qspi_Ip_SetBitfield()
316 uint8 width in Qspi_Ip_GetBitfield() argument
330 mask = (1UL << (uint32)width) - 1UL; in Qspi_Ip_GetBitfield()
343 uint8 width, in Qspi_Ip_UpdateStatusReg() argument
358 if (value != Qspi_Ip_GetBitfield(data, statusConfig->regSize, offset, width)) in Qspi_Ip_UpdateStatusReg()
360 Qspi_Ip_SetBitfield(data, statusConfig->regSize, offset, width, value); in Qspi_Ip_UpdateStatusReg()
384 uint8 width, in Qspi_Ip_CheckStatusReg() argument
398 *value = (uint8)Qspi_Ip_GetBitfield(data, statusConfig->regSize, offset, width); in Qspi_Ip_CheckStatusReg()
649 fieldVal = Qspi_Ip_GetBitfield(value, operation->size, operation->shift, operation->width); in Qspi_Ip_InitRMWReg()
[all …]
/hal_nxp-latest/s32/drivers/s32ze/Mem_EXFLS/src/
DQspi_Ip.c316 uint8 width, in Qspi_Ip_SetBitfield() argument
330 mask = ((1UL << (uint32)width) - 1UL) << (uint32)shift; in Qspi_Ip_SetBitfield()
350 uint8 width in Qspi_Ip_GetBitfield() argument
364 mask = (1UL << (uint32)width) - 1UL; in Qspi_Ip_GetBitfield()
377 uint8 width, in Qspi_Ip_UpdateStatusReg() argument
392 if (value != Qspi_Ip_GetBitfield(data, statusConfig->regSize, offset, width)) in Qspi_Ip_UpdateStatusReg()
394 Qspi_Ip_SetBitfield(data, statusConfig->regSize, offset, width, value); in Qspi_Ip_UpdateStatusReg()
418 uint8 width, in Qspi_Ip_CheckStatusReg() argument
432 *value = (uint8)Qspi_Ip_GetBitfield(data, statusConfig->regSize, offset, width); in Qspi_Ip_CheckStatusReg()
690 fieldVal = Qspi_Ip_GetBitfield(value, operation->size, operation->shift, operation->width); in Qspi_Ip_InitRMWReg()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/components/video/i2c/
Dfsl_video_i2c.c59 uint8_t width = (uint8_t)regWidth; in VIDEO_I2C_ReadReg() local
66 while (0U != (width--)) in VIDEO_I2C_ReadReg()
68 ((uint8_t *)value)[i++] = data[width]; in VIDEO_I2C_ReadReg()

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