Searched refs:rxBuffSizeAlign (Results 1 – 8 of 8) sorted by relevance
696 …reg |= ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y(buffCfg->rxBuffSizeAlign >> ENET_QOS_RXBUFF_IGNORELSB_BI… in ENET_QOS_RxDescriptorsInit()1574 handle->rxBdRing[count].rxBuffSizeAlign = buffConfig->rxBuffSizeAlign; in ENET_QOS_CreateHandler()2304 rxBdRing->rxBuffSizeAlign); in ENET_QOS_ReadFrame()2307 ENET_QOS_DcacheInvalidateByRange(buff1Addr, rxBdRing->rxBuffSizeAlign); in ENET_QOS_ReadFrame()2320 rxBdRing->rxBuffSizeAlign); in ENET_QOS_ReadFrame()2323 rxBdRing->rxBuffSizeAlign); in ENET_QOS_ReadFrame()2326 ENET_QOS_DcacheInvalidateByRange(buff1Addr, rxBdRing->rxBuffSizeAlign); in ENET_QOS_ReadFrame()2328 ENET_QOS_DcacheInvalidateByRange(buff2Addr, rxBdRing->rxBuffSizeAlign); in ENET_QOS_ReadFrame()2348 if (len > rxBdRing->rxBuffSizeAlign) in ENET_QOS_ReadFrame()2353 rxBdRing->rxBuffSizeAlign); in ENET_QOS_ReadFrame()[all …]
561 uint32_t rxBuffSizeAlign; /*!< Aligned receive data buffer size. */ member657 uint32_t rxBuffSizeAlign; /*!< Receive buffer size. */ member
404 reg |= ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ(buffCfg->rxBuffSizeAlign >> ENET_RXBUFF_IGNORELSB_BITS); in ENET_RxDescriptorsInit()891 handle->rxBdRing[count].rxBuffSizeAlign = buffConfig->rxBuffSizeAlign; in ENET_CreateHandler()1292 if (len > rxBdRing->rxBuffSizeAlign) in ENET_ReadFrame()1295 rxBdRing->rxBuffSizeAlign); in ENET_ReadFrame()1296 offset += rxBdRing->rxBuffSizeAlign; in ENET_ReadFrame()1298 len - rxBdRing->rxBuffSizeAlign); in ENET_ReadFrame()1368 rxBdRing->rxBuffSizeAlign); in ENET_ReadFrame()1369 offset += rxBdRing->rxBuffSizeAlign; in ENET_ReadFrame()1373 rxBdRing->rxBuffSizeAlign); in ENET_ReadFrame()1374 offset += rxBdRing->rxBuffSizeAlign; in ENET_ReadFrame()[all …]
412 uint32_t rxBuffSizeAlign; /*!< Aligned receive data buffer size. */ member493 uint32_t rxBuffSizeAlign; /*!< Receive buffer size. */ member
405 …reg |= ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_13_Y(buffCfg->rxBuffSizeAlign >> ENET_RXBUFF_IGNORELSB_BIT… in ENET_RxDescriptorsInit()891 handle->rxBdRing[count].rxBuffSizeAlign = buffConfig->rxBuffSizeAlign; in ENET_CreateHandler()1414 if (len > rxBdRing->rxBuffSizeAlign) in ENET_ReadFrame()1417 rxBdRing->rxBuffSizeAlign); in ENET_ReadFrame()1418 offset += rxBdRing->rxBuffSizeAlign; in ENET_ReadFrame()1420 len - rxBdRing->rxBuffSizeAlign); in ENET_ReadFrame()1490 rxBdRing->rxBuffSizeAlign); in ENET_ReadFrame()1491 offset += rxBdRing->rxBuffSizeAlign; in ENET_ReadFrame()1495 rxBdRing->rxBuffSizeAlign); in ENET_ReadFrame()1496 offset += rxBdRing->rxBuffSizeAlign; in ENET_ReadFrame()[all …]
437 uint32_t rxBuffSizeAlign; /*!< Aligned receive data buffer size. */ member519 uint32_t rxBuffSizeAlign; /*!< Receive buffer size. */ member
486 assert(buffCfg->rxBuffSizeAlign * buffCfg->rxBdNumber > config->rxMaxFrameLen); in ENET_SetHandler()489 handle->rxBuffSizeAlign[count] = buffCfg->rxBuffSizeAlign; in ENET_SetHandler()693 base->MRBR = (uint32_t)bufferConfig->rxBuffSizeAlign; in ENET_SetMacController()711 base->MRBR1 = (uint32_t)buffCfg->rxBuffSizeAlign; in ENET_SetMacController()726 base->MRBR2 = (uint32_t)buffCfg->rxBuffSizeAlign; in ENET_SetMacController()870 assert(buffCfg->rxBuffSizeAlign >= ENET_RX_MIN_BUFFERSIZE); in ENET_SetRxBufferDescriptors()898 … rxBuffer = (uintptr_t)buffCfg->rxBufferAlign + (uintptr_t)count * buffCfg->rxBuffSizeAlign; in ENET_SetRxBufferDescriptors()908 assert((uint64_t)rxBuffer + buffCfg->rxBuffSizeAlign - 1U <= UINT32_MAX); in ENET_SetRxBufferDescriptors()913 DCACHE_InvalidateByRange(rxBuffer, (uint32_t)buffCfg->rxBuffSizeAlign); in ENET_SetRxBufferDescriptors()1757 DCACHE_InvalidateByRange(address, handle->rxBuffSizeAlign[ringId]); in ENET_ReadFrame()[all …]
559 uint16_t rxBuffSizeAlign; /*!< Aligned receive data buffer size. */ member700 uint16_t rxBuffSizeAlign[FSL_FEATURE_ENET_QUEUE]; /*!< Receive buffer size alignment. */ member
