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Searched refs:regAddr (Results 1 – 25 of 109) sorted by relevance

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/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/include/
DRegLockMacros.h303 #define SLBR_ADDR32(baseAddr, regAddr, prot_mem) (((uint32)(baseAddr)) + ((prot_mem) * SLBR_ADDR_O… argument
304 … ENDIANNESS((uint32)((((uint32)(regAddr)) - ((uint32)(baseAddr)))>>0x2U)))
391 #define REG_SET_SOFT_LOCK8(baseAddr, regAddr, prot_mem) \ argument
393 RLM_REG_WRITE8(SLBR_ADDR32((baseAddr), (regAddr), (prot_mem)), \
394 …(uint8)(SLBR_SET_BIT_8BIT_REG_MASK_U8 >> ((((regAddr) - (baseAddr)) & MODULO_4_BIT_MASK_U32) ^ SLB…
397 #define REG_SET_SOFT_LOCK8(baseAddr, regAddr, prot_mem)
401 #define REG_SET_SOFT_LOCK16(baseAddr, regAddr, prot_mem) \ argument
403 RLM_REG_WRITE8(SLBR_ADDR32((baseAddr), (regAddr), (prot_mem)), \
404 …(uint8)(SLBR_SET_BIT_16BIT_REG_MASK_U8 >> ((((regAddr) - (baseAddr)) & MODULO_4_BIT_MASK_U32) ^ SL…
407 #define REG_SET_SOFT_LOCK16(baseAddr, regAddr, prot_mem)
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/hal_nxp-latest/s32/drivers/s32k3/BaseNXP/include/
DRegLockMacros.h303 #define SLBR_ADDR32(baseAddr, regAddr, prot_mem) (((uint32)(baseAddr)) + ((prot_mem) * SLBR_ADDR_O… argument
304 … ENDIANNESS((uint32)((((uint32)(regAddr)) - ((uint32)(baseAddr)))>>0x2U)))
391 #define REG_SET_SOFT_LOCK8(baseAddr, regAddr, prot_mem) \ argument
393 RLM_REG_WRITE8(SLBR_ADDR32((baseAddr), (regAddr), (prot_mem)), \
394 …(uint8)(SLBR_SET_BIT_8BIT_REG_MASK_U8 >> ((((regAddr) - (baseAddr)) & MODULO_4_BIT_MASK_U32) ^ SLB…
397 #define REG_SET_SOFT_LOCK8(baseAddr, regAddr, prot_mem)
401 #define REG_SET_SOFT_LOCK16(baseAddr, regAddr, prot_mem) \ argument
403 RLM_REG_WRITE8(SLBR_ADDR32((baseAddr), (regAddr), (prot_mem)), \
404 …(uint8)(SLBR_SET_BIT_16BIT_REG_MASK_U8 >> ((((regAddr) - (baseAddr)) & MODULO_4_BIT_MASK_U32) ^ SL…
407 #define REG_SET_SOFT_LOCK16(baseAddr, regAddr, prot_mem)
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/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/include/
DRegLockMacros.h302 #define SLBR_ADDR32(baseAddr, regAddr, prot_mem) (((uint32)(baseAddr)) + ((prot_mem) * SLBR_ADDR_O… argument
303 … ENDIANNESS((uint32)((((uint32)(regAddr)) - ((uint32)(baseAddr)))>>0x2U)))
390 #define REG_SET_SOFT_LOCK8(baseAddr, regAddr, prot_mem) \ argument
392 RLM_REG_WRITE8(SLBR_ADDR32((baseAddr), (regAddr), (prot_mem)), \
393 …(uint8)(SLBR_SET_BIT_8BIT_REG_MASK_U8 >> ((((regAddr) - (baseAddr)) & MODULO_4_BIT_MASK_U32) ^ SLB…
396 #define REG_SET_SOFT_LOCK8(baseAddr, regAddr, prot_mem)
400 #define REG_SET_SOFT_LOCK16(baseAddr, regAddr, prot_mem) \ argument
402 RLM_REG_WRITE8(SLBR_ADDR32((baseAddr), (regAddr), (prot_mem)), \
403 …(uint8)(SLBR_SET_BIT_16BIT_REG_MASK_U8 >> ((((regAddr) - (baseAddr)) & MODULO_4_BIT_MASK_U32) ^ SL…
406 #define REG_SET_SOFT_LOCK16(baseAddr, regAddr, prot_mem)
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/hal_nxp-latest/mcux/mcux-sdk/components/pca9422/
Dfsl_pca9422.c1217 uint8_t regVal, regAddr; in PCA9422_InitRegulator() local
1233 regAddr = PCA9422_INT1_MASK; in PCA9422_InitRegulator()
1234 result = PCA9422_WriteRegs(handle, regAddr, &regVal, 1U); in PCA9422_InitRegulator()
1241 regAddr = PCA9422_RESET_CTRL; in PCA9422_InitRegulator()
1242 result = PCA9422_WriteRegs(handle, regAddr, &regVal, 1U); in PCA9422_InitRegulator()
1249 regAddr = PCA9422_PWR_SEQ_CTRL; in PCA9422_InitRegulator()
1250 result = PCA9422_WriteRegs(handle, regAddr, &regVal, 1U); in PCA9422_InitRegulator()
1257 regAddr = PCA9422_SYS_CFG1; in PCA9422_InitRegulator()
1258 result = PCA9422_WriteRegs(handle, regAddr, &regVal, 1U); in PCA9422_InitRegulator()
1265 regAddr = PCA9422_SYS_CFG2; in PCA9422_InitRegulator()
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/hal_nxp-latest/mcux/mcux-sdk/drivers/netc/
Dfsl_netc_mdio.c96 static status_t NETC_PEMDIO_Write(netc_mdio_hw_t *base, uint8_t phyAddr, uint8_t regAddr, uint16_t … in NETC_PEMDIO_Write() argument
101 …IO_CTL = ENETC_PF_EMDIO_EMDIO_CTL_PORT_ADDR(phyAddr) | ENETC_PF_EMDIO_EMDIO_CTL_DEV_ADDR(regAddr); in NETC_PEMDIO_Write()
116 static status_t NETC_PEMDIO_Read(netc_mdio_hw_t *base, uint8_t phyAddr, uint8_t regAddr, uint16_t *… in NETC_PEMDIO_Read() argument
122 ENETC_PF_EMDIO_EMDIO_CTL_DEV_ADDR(regAddr); in NETC_PEMDIO_Read()
138 netc_mdio_hw_t *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t data) in NETC_PEMDIO_C45Write() argument
142 base->EMDIO_ADDR = ENETC_PF_EMDIO_EMDIO_ADDR_REGADDR(regAddr); in NETC_PEMDIO_C45Write()
162 netc_mdio_hw_t *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t *pData) in NETC_PEMDIO_C45Read() argument
166 base->EMDIO_ADDR = ENETC_PF_EMDIO_EMDIO_ADDR_REGADDR(regAddr); in NETC_PEMDIO_C45Read()
233 static void NETC_PIMDIO_Write(NETC_ETH_LINK_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t … in NETC_PIMDIO_Write() argument
236 …TL = NETC_ETH_LINK_PM0_MDIO_CTL_PORT_ADDR(phyAddr) | NETC_ETH_LINK_PM0_MDIO_CTL_DEV_ADDR(regAddr); in NETC_PIMDIO_Write()
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Dfsl_netc_mdio.h182 status_t NETC_MDIOWrite(netc_mdio_handle_t *handle, uint8_t phyAddr, uint8_t regAddr, uint16_t data…
193 status_t NETC_MDIORead(netc_mdio_handle_t *handle, uint8_t phyAddr, uint8_t regAddr, uint16_t *pDat…
206 netc_mdio_handle_t *handle, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t data);
219 … netc_mdio_handle_t *handle, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t *pData);
/hal_nxp-latest/mcux/mcux-sdk/drivers/trdc_1/
Dfsl_trdc.c689 …uint32_t regAddr = (uint32_t) & (TRDC_MRC_BASE(base, config->mrcIdx)->MRC_DOM0_RGD_W[config->regio… in TRDC_MrcSetRegionDescriptorConfig() local
691 regAddr += TRDC_MRC_DOMAIN_INCREMENT * config->domainIdx; in TRDC_MrcSetRegionDescriptorConfig()
696 *(uint32_t *)regAddr = data; in TRDC_MrcSetRegionDescriptorConfig()
699 regAddr += 4U; in TRDC_MrcSetRegionDescriptorConfig()
702 *(uint32_t *)regAddr = data; in TRDC_MrcSetRegionDescriptorConfig()
842 …uint32_t regAddr = (uint32_t) & (TRDC_MBC_BASE(base, config->mbcIdx)->MBC_DOM0_MEM0_BLK_CFG_W[0… in TRDC_MbcSetMemoryBlockConfig() local
849 …regAddr += (TRDC_MBC_DOMAIN_INCREMENT * config->domainIdx + TRDC_MBC_SLAVE_INCREMENT(config->slave… in TRDC_MbcSetMemoryBlockConfig()
851 configWord = configWord | (*(uint32_t *)regAddr & ~(0xFUL << shift)); in TRDC_MbcSetMemoryBlockConfig()
852 *(uint32_t *)regAddr = configWord; in TRDC_MbcSetMemoryBlockConfig()
/hal_nxp-latest/mcux/mcux-sdk/drivers/trdc/
Dfsl_trdc.c682 …uint32_t regAddr = (uint32_t) & (base->MRC_INDEX[config->mrcIdx].MRC_DOM0_RGD_W[config->regionIdx]… in TRDC_MrcSetRegionDescriptorConfig() local
684 regAddr += TRDC_MRC_DOMAIN_INCREMENT * config->domainIdx; in TRDC_MrcSetRegionDescriptorConfig()
689 *(uint32_t *)regAddr = data; in TRDC_MrcSetRegionDescriptorConfig()
692 regAddr += 4U; in TRDC_MrcSetRegionDescriptorConfig()
695 *(uint32_t *)regAddr = data; in TRDC_MrcSetRegionDescriptorConfig()
828 …uint32_t regAddr = (uint32_t) & (base->MBC_INDEX[config->mbcIdx].MBC_DOM0_MEM0_BLK_CFG_W[0]… in TRDC_MbcSetMemoryBlockConfig() local
841 regAddr += (TRDC_MBC_DOMAIN_INCREMENT * config->domainIdx + slaveIncrement) + in TRDC_MbcSetMemoryBlockConfig()
843 configWord = configWord | (*(uint32_t *)regAddr & ~(0xFUL << shift)); in TRDC_MbcSetMemoryBlockConfig()
844 *(uint32_t *)regAddr = configWord; in TRDC_MbcSetMemoryBlockConfig()
/hal_nxp-latest/mcux/mcux-sdk/components/phy/
Dfsl_phy.h85 typedef status_t (*mdioWrite)(uint8_t phyAddr, uint8_t regAddr, uint16_t data);
88 typedef status_t (*mdioRead)(uint8_t phyAddr, uint8_t regAddr, uint16_t *pData);
91 typedef status_t (*mdioWriteExt)(uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t data…
94 typedef status_t (*mdioReadExt)(uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t *pDat…
145 status_t (*phyWriteC45)(phy_handle_t *handle, uint8_t devAddr, uint16_t regAddr, uint16_t data);
146 … status_t (*phyReadC45)(phy_handle_t *handle, uint8_t devAddr, uint16_t regAddr, uint16_t *pdata);
/hal_nxp-latest/mcux/mcux-sdk/drivers/enet/
Dfsl_enet.h1000 ENET_Type *base, uint8_t phyAddr, uint8_t regAddr, enet_mii_write_t operation, uint16_t data) in ENET_StartSMIWrite() argument
1002 …MMFR = ENET_MMFR_ST(1U) | ENET_MMFR_OP(operation) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(regAddr) | in ENET_StartSMIWrite()
1018 static inline void ENET_StartSMIRead(ENET_Type *base, uint8_t phyAddr, uint8_t regAddr, enet_mii_re… in ENET_StartSMIRead() argument
1021 …ENET_MMFR_ST(1U) | ENET_MMFR_OP(operation) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(regAddr) | ENET_… in ENET_StartSMIRead()
1034 status_t ENET_MDIOWrite(ENET_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t data);
1046 status_t ENET_MDIORead(ENET_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t *pData);
1061 …d ENET_StartExtC45SMIWriteReg(ENET_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr) in ENET_StartExtC45SMIWriteReg() argument
1064 ENET_MMFR_RA(devAddr) | ENET_MMFR_TA(2) | ENET_MMFR_DATA(regAddr); in ENET_StartExtC45SMIWriteReg()
1113 status_t ENET_MDIOC45Write(ENET_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, ui…
1126 status_t ENET_MDIOC45Read(ENET_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uin…
/hal_nxp-latest/mcux/mcux-sdk/boards/mimxrt685audevk/
Dboard.c35 static status_t flexspi_hyper_ram_write_mcr(FLEXSPI_Type *base, uint8_t regAddr, uint32_t *mrVal);
36 static status_t flexspi_hyper_ram_get_mcr(FLEXSPI_Type *base, uint8_t regAddr, uint32_t *mrVal);
57 static status_t flexspi_hyper_ram_write_mcr(FLEXSPI_Type *base, uint8_t regAddr, uint32_t *mrVal) in flexspi_hyper_ram_write_mcr() argument
63 flashXfer.deviceAddress = regAddr; in flexspi_hyper_ram_write_mcr()
76 static status_t flexspi_hyper_ram_get_mcr(FLEXSPI_Type *base, uint8_t regAddr, uint32_t *mrVal) in flexspi_hyper_ram_get_mcr() argument
82 flashXfer.deviceAddress = regAddr; in flexspi_hyper_ram_get_mcr()
/hal_nxp-latest/mcux/mcux-sdk/drivers/enet_qos/
Dfsl_enet_qos.h975 void ENET_QOS_StartSMIWrite(ENET_QOS_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t data);
986 void ENET_QOS_StartSMIRead(ENET_QOS_Type *base, uint8_t phyAddr, uint8_t regAddr);
1000 ENET_QOS_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t data);
1012 …T_QOS_StartExtC45SMIRead(ENET_QOS_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr);
1024 status_t ENET_QOS_MDIOWrite(ENET_QOS_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t data);
1036 status_t ENET_QOS_MDIORead(ENET_QOS_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t *pData);
1049 …OC45Write(ENET_QOS_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t data);
1063 ENET_QOS_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t *pData);
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE02Z4/drivers/
Dfsl_clock.h366 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_EnableClock() local
367 (*(volatile uint32_t *)regAddr) |= (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name)); in CLOCK_EnableClock()
377 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_DisableClock() local
378 (*(volatile uint32_t *)regAddr) &= ~(1UL << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name)); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC041/drivers/
Dfsl_clock.h358 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_EnableClock() local
359 (*(volatile uint32_t *)regAddr) |= (1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name)); in CLOCK_EnableClock()
369 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_DisableClock() local
370 (*(volatile uint32_t *)regAddr) &= ~(1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name)); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/components/phy/device/phyksz8041/
Dfsl_phyksz8041.c32 #define PHY_KSZ8041_WRITE(handle, regAddr, data) \ argument
33 ((phy_ksz8041_resource_t *)(handle)->resource)->write((handle)->phyAddr, regAddr, data)
34 #define PHY_KSZ8041_READ(handle, regAddr, pData) \ argument
35 ((phy_ksz8041_resource_t *)(handle)->resource)->read((handle)->phyAddr, regAddr, pData)
/hal_nxp-latest/mcux/mcux-sdk/components/phy/device/phylan8720a/
Dfsl_phylan8720a.c38 #define PHY_LAN8720A_WRITE(handle, regAddr, data) \ argument
39 ((phy_lan8720a_resource_t *)(handle)->resource)->write((handle)->phyAddr, regAddr, data)
40 #define PHY_LAN8720A_READ(handle, regAddr, pData) \ argument
41 ((phy_lan8720a_resource_t *)(handle)->resource)->read((handle)->phyAddr, regAddr, pData)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE04Z1284/drivers/
Dfsl_clock.h387 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_EnableClock() local
388 (*(volatile uint32_t *)regAddr) |= (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name)); in CLOCK_EnableClock()
398 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_DisableClock() local
399 (*(volatile uint32_t *)regAddr) &= ~(1UL << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name)); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE04Z4/drivers/
Dfsl_clock.h365 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_EnableClock() local
366 (*(volatile uint32_t *)regAddr) |= (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name)); in CLOCK_EnableClock()
376 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_DisableClock() local
377 (*(volatile uint32_t *)regAddr) &= ~(1UL << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name)); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE06Z4/drivers/
Dfsl_clock.h387 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_EnableClock() local
388 (*(volatile uint32_t *)regAddr) |= (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name)); in CLOCK_EnableClock()
398 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_DisableClock() local
399 (*(volatile uint32_t *)regAddr) &= ~(1UL << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name)); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/components/phy/device/phylan8741/
Dfsl_phylan8741.c39 #define PHY_LAN8741_WRITE(handle, regAddr, data) \ argument
40 ((phy_lan8741_resource_t *)(handle)->resource)->write((handle)->phyAddr, regAddr, data)
41 #define PHY_LAN8741_READ(handle, regAddr, pData) \ argument
42 ((phy_lan8741_resource_t *)(handle)->resource)->read((handle)->phyAddr, regAddr, pData)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/drivers/
Dfsl_i2s_bridge.c38 static void SYSCTL1_UpdateRegister(SYSCTL1_Type *base, volatile uint32_t *regAddr, uint32_t value) in SYSCTL1_UpdateRegister() argument
43 *regAddr = value; in SYSCTL1_UpdateRegister()
48 *regAddr = value; in SYSCTL1_UpdateRegister()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/drivers/
Dfsl_i2s_bridge.c38 static void SYSCTL1_UpdateRegister(SYSCTL1_Type *base, volatile uint32_t *regAddr, uint32_t value) in SYSCTL1_UpdateRegister() argument
43 *regAddr = value; in SYSCTL1_UpdateRegister()
48 *regAddr = value; in SYSCTL1_UpdateRegister()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/drivers/
Dfsl_i2s_bridge.c38 static void SYSCTL1_UpdateRegister(SYSCTL1_Type *base, volatile uint32_t *regAddr, uint32_t value) in SYSCTL1_UpdateRegister() argument
43 *regAddr = value; in SYSCTL1_UpdateRegister()
48 *regAddr = value; in SYSCTL1_UpdateRegister()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt685/
Dboard.c38 static status_t flexspi_hyper_ram_write_mcr(FLEXSPI_Type *base, uint8_t regAddr, uint32_t *mrVal);
39 static status_t flexspi_hyper_ram_get_mcr(FLEXSPI_Type *base, uint8_t regAddr, uint32_t *mrVal);
64 static status_t flexspi_hyper_ram_write_mcr(FLEXSPI_Type *base, uint8_t regAddr, uint32_t *mrVal) in flexspi_hyper_ram_write_mcr() argument
70 flashXfer.deviceAddress = regAddr; in flexspi_hyper_ram_write_mcr()
83 static status_t flexspi_hyper_ram_get_mcr(FLEXSPI_Type *base, uint8_t regAddr, uint32_t *mrVal) in flexspi_hyper_ram_get_mcr() argument
89 flashXfer.deviceAddress = regAddr; in flexspi_hyper_ram_get_mcr()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC142/drivers/
Dfsl_clock.h418 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_EnableClock() local
419 (*(volatile uint32_t *)regAddr) |= (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name)); in CLOCK_EnableClock()
429 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_DisableClock() local
430 (*(volatile uint32_t *)regAddr) &= ~(1UL << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name)); in CLOCK_DisableClock()

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