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Searched refs:pfd_n (Results 1 – 2 of 2) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX9131/drivers/
Dfsl_clock.h102 static inline void CLOCK_PllPfdInit(PLL_Type *pll, uint32_t pfd_n, const fracn_pll_pfd_init_t *pfd_… in CLOCK_PllPfdInit() argument
105 pll->DFS[pfd_n].DFS_CTRL.SET = PLL_DFS_BYPASS_EN_MASK; in CLOCK_PllPfdInit()
107 pll->DFS[pfd_n].DFS_CTRL.CLR = PLL_DFS_CLKOUT_EN_MASK | PLL_DFS_ENABLE_MASK; in CLOCK_PllPfdInit()
109 pll->DFS[pfd_n].DFS_DIV.RW = PLL_DFS_MFI(pfd_cfg->mfi) | PLL_DFS_MFN(pfd_cfg->mfn); in CLOCK_PllPfdInit()
111 pll->DFS[pfd_n].DFS_CTRL.SET = PLL_DFS_CLKOUT_EN_MASK; in CLOCK_PllPfdInit()
115 pll->DFS[pfd_n].DFS_CTRL.SET = PLL_DFS_CLKOUT_DIVBY2_EN_MASK; in CLOCK_PllPfdInit()
118 pll->DFS[pfd_n].DFS_CTRL.SET = PLL_DFS_ENABLE_MASK; in CLOCK_PllPfdInit()
119 while (((pll->DFS_STATUS & PLL_DFS_STATUS_DFS_OK_MASK) & (1UL << pfd_n)) == 0UL) in CLOCK_PllPfdInit()
123 pll->DFS[pfd_n].DFS_CTRL.CLR = PLL_DFS_BYPASS_EN_MASK; in CLOCK_PllPfdInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX9352/drivers/
Dfsl_clock.h102 static inline void CLOCK_PllPfdInit(PLL_Type *pll, uint32_t pfd_n, const fracn_pll_pfd_init_t *pfd_… in CLOCK_PllPfdInit() argument
105 pll->DFS[pfd_n].DFS_CTRL.SET = PLL_DFS_BYPASS_EN_MASK; in CLOCK_PllPfdInit()
107 pll->DFS[pfd_n].DFS_CTRL.CLR = PLL_DFS_CLKOUT_EN_MASK | PLL_DFS_ENABLE_MASK; in CLOCK_PllPfdInit()
109 pll->DFS[pfd_n].DFS_DIV.RW = PLL_DFS_MFI(pfd_cfg->mfi) | PLL_DFS_MFN(pfd_cfg->mfn); in CLOCK_PllPfdInit()
111 pll->DFS[pfd_n].DFS_CTRL.SET = PLL_DFS_CLKOUT_EN_MASK; in CLOCK_PllPfdInit()
115 pll->DFS[pfd_n].DFS_CTRL.SET = PLL_DFS_CLKOUT_DIVBY2_EN_MASK; in CLOCK_PllPfdInit()
118 pll->DFS[pfd_n].DFS_CTRL.SET = PLL_DFS_ENABLE_MASK; in CLOCK_PllPfdInit()
119 while (((pll->DFS_STATUS & PLL_DFS_STATUS_DFS_OK_MASK) & (1UL << pfd_n)) == 0UL) in CLOCK_PllPfdInit()
123 pll->DFS[pfd_n].DFS_CTRL.CLR = PLL_DFS_BYPASS_EN_MASK; in CLOCK_PllPfdInit()