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Searched refs:kResc_SRAM_CPU0_DCACHE (Results 1 – 6 of 6) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT735S/
Dfsl_pm_device.h150 kResc_SRAM_CPU0_DCACHE, /*!< CPU0 System cache RAM */ enumerator
309 #define PM_RESC_SRAM_CPU0_DCACHE_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_CPU0_DCACHE)
333 …PM_RESC_SRAM_CPU0_DCACHE_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_CPU0_DCACHE)
Dfsl_pm_device.c241 [kResc_SRAM_CPU0_DCACHE - RESC_GROUP_SRAMS_START] = {5U, PMC_PDSLEEPCFG4_CPU0_SCACHE_MASK},
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT758S/
Dfsl_pm_device.h150 kResc_SRAM_CPU0_DCACHE, /*!< CPU0 System cache RAM */ enumerator
309 #define PM_RESC_SRAM_CPU0_DCACHE_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_CPU0_DCACHE)
333 …PM_RESC_SRAM_CPU0_DCACHE_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_CPU0_DCACHE)
Dfsl_pm_device.c241 [kResc_SRAM_CPU0_DCACHE - RESC_GROUP_SRAMS_START] = {5U, PMC_PDSLEEPCFG4_CPU0_SCACHE_MASK},
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT798S/
Dfsl_pm_device.h150 kResc_SRAM_CPU0_DCACHE, /*!< CPU0 System cache RAM */ enumerator
309 #define PM_RESC_SRAM_CPU0_DCACHE_ACTIVE PM_ENCODE_RESC(PM_RESOURCE_FULL_ON, kResc_SRAM_CPU0_DCACHE)
333 …PM_RESC_SRAM_CPU0_DCACHE_RETENTION PM_ENCODE_RESC(PM_RESOURCE_PARTABLE_ON1, kResc_SRAM_CPU0_DCACHE)
Dfsl_pm_device.c241 [kResc_SRAM_CPU0_DCACHE - RESC_GROUP_SRAMS_START] = {5U, PMC_PDSLEEPCFG4_CPU0_SCACHE_MASK},