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Searched refs:eMIOS_WSC1_FEN_MASK (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-latest/s32/drivers/s32ze/Mcl/src/
DEmios_Mcl_Ip_Irq.c930 … if (0U != ((Emios_Ip_paxBase[Instance]->CH.WSC[Channel/2].WSC1) & ((uint32)eMIOS_WSC1_FEN_MASK))) in Emios_Gpt_Wsc_IrqHandler()
960 … if (0U != ((Emios_Ip_paxBase[Instance]->CH.WSC[Channel/2].WSC1) & ((uint32)eMIOS_WSC1_FEN_MASK))) in Emios_Icu_Wsc_IrqHandler()
990 … if (0U != ((Emios_Ip_paxBase[Instance]->CH.WSC[Channel/2].WSC1) & ((uint32)eMIOS_WSC1_FEN_MASK))) in Emios_Ocu_Wsc_IrqHandler()
1020 … if (0U != ((Emios_Ip_paxBase[Instance]->CH.WSC[Channel/2].WSC1) & ((uint32)eMIOS_WSC1_FEN_MASK))) in Emios_Pwm_Wsc_IrqHandler()
/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_EMIOS.h663 #define eMIOS_WSC1_FEN_MASK (0x20000U) macro
666 … (((uint32_t)(((uint32_t)(x)) << eMIOS_WSC1_FEN_SHIFT)) & eMIOS_WSC1_FEN_MASK)
/hal_nxp-latest/s32/drivers/s32ze/Icu/src/
DEmios_Icu_Ip.c2004 s_emiosBase[instance]->CH.WSC[hwWSChannelId].WSC1 |= (uint32)eMIOS_WSC1_FEN_MASK; in Emios_Icu_Ip_WheelSpeedEnableInterrupt()
2030 s_emiosBase[instance]->CH.WSC[hwWSChannelId].WSC1 &= ~(uint32)eMIOS_WSC1_FEN_MASK; in Emios_Icu_Ip_WheelSpeedDisableInterrupt()