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/hal_nxp-latest/mcux/mcux-sdk/boards/frdmke17z512/
Dclock_config.c70 .div2 = kSCG_AsyncClkDivBy2, in CLOCK_CONFIG_FircSafeConfig()
170 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
176 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
182 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
189 .div2 = kSCG_AsyncClkDivBy2, /* Low Power FLL Clock Divider 2: divided by 2 */
280 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
286 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
292 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
299 .div2 = kSCG_AsyncClkDivBy2, /* Low Power FLL Clock Divider 2: divided by 2 */
382 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
[all …]
/hal_nxp-latest/mcux/mcux-sdk/boards/twrke18f/
Dclock_config.c73 .div2 = kSCG_AsyncClkDivBy2, in CLOCK_CONFIG_FircSafeConfig()
170 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
176 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
182 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
190 .div2 = kSCG_AsyncClkDivBy2, /* System PLL Clock Divider 2: divided by 2 */
282 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
288 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
294 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
302 .div2 = kSCG_AsyncClkDivBy2, /* System PLL Clock Divider 2: divided by 2 */
402 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
[all …]
/hal_nxp-latest/mcux/mcux-sdk/boards/frdmke16z/
Dclock_config.c73 .div2 = kSCG_AsyncClkDivBy2, in CLOCK_CONFIG_FircSafeConfig()
170 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
176 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
182 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
189 .div2 = kSCG_AsyncClkDivBy2, /* Low Power FLL Clock Divider 2: divided by 2 */
278 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
284 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
290 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
297 .div2 = kSCG_AsyncClkDivBy2, /* Low Power FLL Clock Divider 2: divided by 2 */
/hal_nxp-latest/mcux/mcux-sdk/boards/frdmke15z/
Dclock_config.c74 .div2 = kSCG_AsyncClkDivBy2, in CLOCK_CONFIG_FircSafeConfig()
169 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
175 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
181 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
188 .div2 = kSCG_AsyncClkDivBy2, /* Low Power FLL Clock Divider 2: divided by 2 */
274 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
280 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
286 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
293 .div2 = kSCG_AsyncClkDivBy2, /* Low Power FLL Clock Divider 2: divided by 2 */
/hal_nxp-latest/mcux/mcux-sdk/boards/frdmke17z/
Dclock_config.c71 .div2 = kSCG_AsyncClkDivBy2, in CLOCK_CONFIG_FircSafeConfig()
165 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
170 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
175 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
181 .div2 = kSCG_AsyncClkDivBy2, /* Low Power FLL Clock Divider 2: divided by 2 */
266 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
271 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
276 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
282 .div2 = kSCG_AsyncClkDivBy2, /* Low Power FLL Clock Divider 2: divided by 2 */
/hal_nxp-latest/mcux/mcux-sdk/boards/frdmk32l3a6/
Dclock_config.c75 .div2 = kSCG_AsyncClkDivBy2, in CLOCK_CONFIG_FircSafeConfig()
150 … .div2 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 2: Clock output is disabled */
158 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
167 ….div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabl…
250 … .div2 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 2: Clock output is disabled */
258 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
267 ….div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabl…
358 .div2 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 2: divided by 1 */
366 … .div2 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 2: Clock output is disabled */
375 ….div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabl…
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmcimx7ulp/
Dclock_config.c35 .div2 = kSCG_AsyncClkDisable,
48 .div2 = kSCG_AsyncClkDisable,
61 .div2 = kSCG_AsyncClkDisable,
76 .div2 = kSCG_AsyncClkDisable,
93 .div2 = kSCG_AsyncClkDivBy1,
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE16Z4/drivers/
Dfsl_clock.h389 scg_async_clk_div_t div2; /*!< SOSCDIV2 value. */ member
417 scg_async_clk_div_t div2; /*!< SIRCDIV2 value. */ member
496 scg_async_clk_div_t div2; /*!< FIRCDIV2 value. */ member
574 scg_async_clk_div_t div2; /*!< LPFLLDIV2 value. */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z4/drivers/
Dfsl_clock.h385 scg_async_clk_div_t div2; /*!< SOSCDIV2 value. */ member
413 scg_async_clk_div_t div2; /*!< SIRCDIV2 value. */ member
492 scg_async_clk_div_t div2; /*!< FIRCDIV2 value. */ member
570 scg_async_clk_div_t div2; /*!< LPFLLDIV2 value. */ member
Dfsl_clock.c314 SCG->SOSCDIV = SCG_SOSCDIV_SOSCDIV2(config->div2); in CLOCK_InitSysOsc()
459 SCG->SIRCDIV = SCG_SIRCDIV_SIRCDIV2(config->div2); in CLOCK_InitSirc()
599 SCG->FIRCDIV = SCG_FIRCDIV_FIRCDIV2(config->div2); in CLOCK_InitFirc()
762 SCG->LPFLLDIV = SCG_LPFLLDIV_LPFLLDIV2(config->div2); in CLOCK_InitLpFll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z4/drivers/
Dfsl_clock.h377 scg_async_clk_div_t div2; /*!< SOSCDIV2 value. */ member
405 scg_async_clk_div_t div2; /*!< SIRCDIV2 value. */ member
484 scg_async_clk_div_t div2; /*!< FIRCDIV2 value. */ member
562 scg_async_clk_div_t div2; /*!< LPFLLDIV2 value. */ member
Dfsl_clock.c314 SCG->SOSCDIV = SCG_SOSCDIV_SOSCDIV2(config->div2); in CLOCK_InitSysOsc()
459 SCG->SIRCDIV = SCG_SIRCDIV_SIRCDIV2(config->div2); in CLOCK_InitSirc()
599 SCG->FIRCDIV = SCG_FIRCDIV_FIRCDIV2(config->div2); in CLOCK_InitFirc()
762 SCG->LPFLLDIV = SCG_LPFLLDIV_LPFLLDIV2(config->div2); in CLOCK_InitLpFll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z7/drivers/
Dfsl_clock.h400 scg_async_clk_div_t div2; /*!< SOSCDIV2 value. */ member
428 scg_async_clk_div_t div2; /*!< SIRCDIV2 value. */ member
507 scg_async_clk_div_t div2; /*!< FIRCDIV2 value. */ member
586 scg_async_clk_div_t div2; /*!< LPFLLDIV2 value. */ member
Dfsl_clock.c335 SCG->SOSCDIV = SCG_SOSCDIV_SOSCDIV2(config->div2); in CLOCK_InitSysOsc()
480 SCG->SIRCDIV = SCG_SIRCDIV_SIRCDIV2(config->div2); in CLOCK_InitSirc()
620 SCG->FIRCDIV = SCG_FIRCDIV_FIRCDIV2(config->div2); in CLOCK_InitFirc()
778 SCG->LPFLLDIV = SCG_LPFLLDIV_LPFLLDIV2(config->div2); in CLOCK_InitLpFll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z9/drivers/
Dfsl_clock.h409 scg_async_clk_div_t div2; /*!< SOSCDIV2 value. */ member
437 scg_async_clk_div_t div2; /*!< SIRCDIV2 value. */ member
516 scg_async_clk_div_t div2; /*!< FIRCDIV2 value. */ member
597 scg_async_clk_div_t div2; /*!< LPFLLDIV2 value. */ member
Dfsl_clock.c334 SCG->SOSCDIV = SCG_SOSCDIV_SOSCDIV2(config->div2); in CLOCK_InitSysOsc()
479 SCG->SIRCDIV = SCG_SIRCDIV_SIRCDIV2(config->div2); in CLOCK_InitSirc()
619 SCG->FIRCDIV = SCG_FIRCDIV_FIRCDIV2(config->div2); in CLOCK_InitFirc()
782 SCG->LPFLLDIV = SCG_LPFLLDIV_LPFLLDIV2(config->div2); in CLOCK_InitLpFll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z7/drivers/
Dfsl_clock.h435 scg_async_clk_div_t div2; /*!< SOSCDIV2 value. */ member
463 scg_async_clk_div_t div2; /*!< SIRCDIV2 value. */ member
545 scg_async_clk_div_t div2; /*!< FIRCDIV2 value. */ member
626 scg_async_clk_div_t div2; /*!< LPFLLDIV2 value. */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z7/drivers/
Dfsl_clock.h401 scg_async_clk_div_t div2; /*!< SOSCDIV2 value. */ member
429 scg_async_clk_div_t div2; /*!< SIRCDIV2 value. */ member
508 scg_async_clk_div_t div2; /*!< FIRCDIV2 value. */ member
587 scg_async_clk_div_t div2; /*!< LPFLLDIV2 value. */ member
Dfsl_clock.c335 SCG->SOSCDIV = SCG_SOSCDIV_SOSCDIV2(config->div2); in CLOCK_InitSysOsc()
480 SCG->SIRCDIV = SCG_SIRCDIV_SIRCDIV2(config->div2); in CLOCK_InitSirc()
620 SCG->FIRCDIV = SCG_FIRCDIV_FIRCDIV2(config->div2); in CLOCK_InitFirc()
778 SCG->LPFLLDIV = SCG_LPFLLDIV_LPFLLDIV2(config->div2); in CLOCK_InitLpFll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z9/drivers/
Dfsl_clock.h417 scg_async_clk_div_t div2; /*!< SOSCDIV2 value. */ member
445 scg_async_clk_div_t div2; /*!< SIRCDIV2 value. */ member
524 scg_async_clk_div_t div2; /*!< FIRCDIV2 value. */ member
605 scg_async_clk_div_t div2; /*!< LPFLLDIV2 value. */ member
Dfsl_clock.c334 SCG->SOSCDIV = SCG_SOSCDIV_SOSCDIV2(config->div2); in CLOCK_InitSysOsc()
479 SCG->SIRCDIV = SCG_SIRCDIV_SIRCDIV2(config->div2); in CLOCK_InitSirc()
619 SCG->FIRCDIV = SCG_FIRCDIV_FIRCDIV2(config->div2); in CLOCK_InitFirc()
782 SCG->LPFLLDIV = SCG_LPFLLDIV_LPFLLDIV2(config->div2); in CLOCK_InitLpFll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z7/drivers/
Dfsl_clock.h442 scg_async_clk_div_t div2; /*!< SOSCDIV2 value. */ member
470 scg_async_clk_div_t div2; /*!< SIRCDIV2 value. */ member
552 scg_async_clk_div_t div2; /*!< FIRCDIV2 value. */ member
633 scg_async_clk_div_t div2; /*!< LPFLLDIV2 value. */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z7/drivers/
Dfsl_clock.h393 scg_async_clk_div_t div2; /*!< SOSCDIV2 value. */ member
421 scg_async_clk_div_t div2; /*!< SIRCDIV2 value. */ member
503 scg_async_clk_div_t div2; /*!< FIRCDIV2 value. */ member
584 scg_async_clk_div_t div2; /*!< LPFLLDIV2 value. */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z9/drivers/
Dfsl_clock.h416 scg_async_clk_div_t div2; /*!< SOSCDIV2 value. */ member
444 scg_async_clk_div_t div2; /*!< SIRCDIV2 value. */ member
523 scg_async_clk_div_t div2; /*!< FIRCDIV2 value. */ member
604 scg_async_clk_div_t div2; /*!< LPFLLDIV2 value. */ member
Dfsl_clock.c334 SCG->SOSCDIV = SCG_SOSCDIV_SOSCDIV2(config->div2); in CLOCK_InitSysOsc()
479 SCG->SIRCDIV = SCG_SIRCDIV_SIRCDIV2(config->div2); in CLOCK_InitSirc()
619 SCG->FIRCDIV = SCG_FIRCDIV_FIRCDIV2(config->div2); in CLOCK_InitFirc()
782 SCG->LPFLLDIV = SCG_LPFLLDIV_LPFLLDIV2(config->div2); in CLOCK_InitLpFll()

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