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Searched refs:__ASM (Results 1 – 25 of 78) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/CMSIS/Core/Include/
Dcmsis_gcc.h40 #ifndef __ASM
41 #define __ASM __asm macro
117 #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
228 #define __NOP() __ASM volatile ("nop")
234 #define __WFI() __ASM volatile ("wfi":::"memory")
242 #define __WFE() __ASM volatile ("wfe":::"memory")
249 #define __SEV() __ASM volatile ("sev")
260 __ASM volatile ("isb 0xF":::"memory"); in __ISB()
271 __ASM volatile ("dsb 0xF":::"memory"); in __DSB()
282 __ASM volatile ("dmb 0xF":::"memory"); in __DMB()
[all …]
Dcmsis_armclang_ltm.h33 #ifndef __ASM
34 #define __ASM __asm macro
110 #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
276 #define __BKPT(value) __ASM volatile ("bkpt "#value)
423 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); in __RRX()
438 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); in __LDRBT()
453 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); in __LDRHT()
468 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); in __LDRT()
481 __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); in __STRBT()
493 __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); in __STRHT()
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Dcmsis_armclang.h33 #ifndef __ASM
34 #define __ASM __asm macro
110 #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
278 #define __BKPT(value) __ASM volatile ("bkpt "#value)
429 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); in __RRX()
444 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); in __LDRBT()
459 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); in __LDRHT()
474 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); in __LDRT()
487 __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); in __STRBT()
499 __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); in __STRHT()
[all …]
Dcmsis_armcc.h57 #ifndef __ASM
58 #define __ASM __asm macro
208 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) in __REV16()
223 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) in __REVSH()
410 __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) in __RRX()
557 register uint32_t __regControl __ASM("control"); in __get_CONTROL()
569 register uint32_t __regControl __ASM("control"); in __set_CONTROL()
582 register uint32_t __regIPSR __ASM("ipsr"); in __get_IPSR()
594 register uint32_t __regAPSR __ASM("apsr"); in __get_APSR()
606 register uint32_t __regXPSR __ASM("xpsr"); in __get_xPSR()
[all …]
Dcmsis_iccarm.h112 #ifndef __ASM
113 #define __ASM __asm macro
117 #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
632 __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); in __RRX()
872 __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); in __LDRBT()
879 __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); in __LDRHT()
886 __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); in __LDRT()
892 __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); in __STRBT()
897 __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); in __STRHT()
902 __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); in __STRT()
[all …]
Dcmsis_compiler.h70 #ifndef __ASM
71 #define __ASM __asm macro
142 #ifndef __ASM
143 #define __ASM __asm macro
211 #ifndef __ASM
212 #define __ASM _asm macro
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/Include/
Dcmsis_gcc.h40 #ifndef __ASM
41 #define __ASM __asm macro
117 #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
198 __ASM volatile ("cpsie i" : : : "memory"); in __enable_irq()
209 __ASM volatile ("cpsid i" : : : "memory"); in __disable_irq()
222 __ASM volatile ("MRS %0, control" : "=r" (result) ); in __get_CONTROL()
237 __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); in __TZ_get_CONTROL_NS()
250 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); in __set_CONTROL()
262 __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); in __TZ_set_CONTROL_NS()
276 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); in __get_IPSR()
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Dcmsis_armclang_ltm.h37 #ifndef __ASM
38 #define __ASM __asm macro
114 #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
171 __ASM volatile ("MRS %0, control" : "=r" (result) ); in __get_CONTROL()
186 __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); in __TZ_get_CONTROL_NS()
199 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); in __set_CONTROL()
211 __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); in __TZ_set_CONTROL_NS()
225 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); in __get_IPSR()
239 __ASM volatile ("MRS %0, apsr" : "=r" (result) ); in __get_APSR()
253 __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); in __get_xPSR()
[all …]
Dcmsis_armclang.h37 #ifndef __ASM
38 #define __ASM __asm macro
114 #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
170 __ASM volatile ("MRS %0, control" : "=r" (result) ); in __get_CONTROL()
185 __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); in __TZ_get_CONTROL_NS()
198 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); in __set_CONTROL()
210 __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); in __TZ_set_CONTROL_NS()
224 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); in __get_IPSR()
238 __ASM volatile ("MRS %0, apsr" : "=r" (result) ); in __get_APSR()
252 __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); in __get_xPSR()
[all …]
Dcmsis_armcc.h56 #ifndef __ASM
57 #define __ASM __asm macro
161 register uint32_t __regControl __ASM("control"); in __get_CONTROL()
173 register uint32_t __regControl __ASM("control"); in __set_CONTROL()
185 register uint32_t __regIPSR __ASM("ipsr"); in __get_IPSR()
197 register uint32_t __regAPSR __ASM("apsr"); in __get_APSR()
209 register uint32_t __regXPSR __ASM("xpsr"); in __get_xPSR()
221 register uint32_t __regProcessStackPointer __ASM("psp"); in __get_PSP()
233 register uint32_t __regProcessStackPointer __ASM("psp"); in __set_PSP()
245 register uint32_t __regMainStackPointer __ASM("msp"); in __get_MSP()
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Dcmsis_iccarm.h110 #ifndef __ASM
111 #define __ASM __asm macro
115 #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
599 __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); in __RRX()
838 __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); in __LDRBT()
845 __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); in __LDRHT()
852 __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); in __LDRT()
858 __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); in __STRBT()
863 __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); in __STRHT()
868 __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); in __STRT()
[all …]
Dcmsis_compiler.h70 #ifndef __ASM
71 #define __ASM __asm macro
142 #ifndef __ASM
143 #define __ASM __asm macro
211 #ifndef __ASM
212 #define __ASM _asm macro
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/Core_AArch64/Include/
Dcmsis_gcc.h30 #ifndef __ASM
31 #define __ASM __asm macro
95 __ASM volatile ("msr daifclr, #2" : : : "memory"); in __enable_irq()
105 __ASM volatile ("msr daifset, #2" : : : "memory"); in __disable_irq()
152 __ASM volatile ("isb":::"memory"); in __ISB()
164 __ASM volatile ("dsb sy":::"memory"); in __DSB()
176 __ASM volatile ("dmb sy":::"memory"); in __DMB()
210 #define __BKPT(value) __ASM volatile ("brk "#value)
219 __ASM volatile ("nop"); in __NOP()
Dcmsis_compiler.h54 …#define __ASM __asm /*!< asm keyword for ARM Compi… macro
59 …#define __ASM __asm /*!< asm keyword for ARM Compi…
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/RTOS2/RTX/Source/
Drtx_core_ca.h134 __ASM volatile ( in __get_PSP()
328 register uint32_t __r##n __ASM("r"#n)
331 register uint32_t __r##n __ASM("r"#n) = (uint32_t)a
334 register uint32_t __rf __ASM(SVC_RegF) = (uint32_t)f
350 __ASM volatile ("svc 0" : out : in : cl)
450 __ASM volatile ( in atomic_wr8()
496 __ASM volatile ( in atomic_set32()
545 __ASM volatile ( in atomic_clr32()
601 __ASM volatile ( in atomic_chk32_all()
664 __ASM volatile ( in atomic_chk32_any()
[all …]
Drtx_core_cm.h359 register uint32_t __r##n __ASM("r"#n)
362 register uint32_t __r##n __ASM("r"#n) = (uint32_t)a
365 register uint32_t __rf __ASM(SVC_RegF) = (uint32_t)f
381 __ASM volatile ("svc 0" : out : in : cl)
486 __ASM volatile ( in atomic_wr8()
534 __ASM volatile ( in atomic_set32()
594 __ASM volatile ( in atomic_clr32()
661 __ASM volatile ( in atomic_chk32_all()
735 __ASM volatile ( in atomic_chk32_any()
795 __ASM volatile ( in atomic_inc32()
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/hal_nxp-latest/mcux/mcux-sdk/drivers/common/
Dfsl_common_arm.c149 __ASM static void DelayLoop(uint32_t count) in DelayLoop()
160 __ASM volatile(" MOV X0, %0" : : "r"(count)); in DelayLoop()
161 __ASM volatile( in DelayLoop()
177 __ASM volatile(" MOV R0, %0" : : "r"(count)); in DelayLoop()
178 __ASM volatile( in DelayLoop()
Dfsl_common_riscv.c17 __ASM volatile( in DelayLoop()
/hal_nxp-latest/mcux/middleware/mcux-sdk-middleware-connectivity-framework/platform/connected_mcu/
Dfwk_platform.c120 __ASM("NOP"); in PLATFORM_InitNbu()
290 __ASM("NOP"); in PLATFORM_RemoteActiveReq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN6/
Dsystem_MIMX8MN6_ca53.c68 __ASM volatile("mov x0, #(3 << 20) \n\t" in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML8/
Dsystem_MIMX8ML8_ca53.c68 __ASM volatile("mov x0, #(3 << 20) \n\t" in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM6/
Dsystem_MIMX8MM6_ca53.c70 __ASM volatile("mov x0, #(3 << 20) \n\t" in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX9596/
Dsystem_MIMX9596_ca55.c68 __ASM volatile("mov x0, #(3 << 20) \n\t" in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX9131/
Dsystem_MIMX9131.c61 __ASM volatile("mov x0, #(3 << 20) \n\t" in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX9352/
Dsystem_MIMX9352_ca55.c63 __ASM volatile("mov x0, #(3 << 20) \n\t" in SystemInit()

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