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Searched refs:TRNGFCLKDIV_OFFSET (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/drivers/
Dfsl_clock.h852 #define TRNGFCLKDIV_OFFSET 0xAC4 macro
1707 … kCLOCK_DivTrngClk = CLKCTL0_TUPLE_MUXA(TRNGFCLKDIV_OFFSET, 0), /*!< TRNG Clk Divider. */
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/drivers/
Dfsl_clock.h852 #define TRNGFCLKDIV_OFFSET 0xAC4 macro
1707 … kCLOCK_DivTrngClk = CLKCTL0_TUPLE_MUXA(TRNGFCLKDIV_OFFSET, 0), /*!< TRNG Clk Divider. */
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/drivers/
Dfsl_clock.h852 #define TRNGFCLKDIV_OFFSET 0xAC4 macro
1707 … kCLOCK_DivTrngClk = CLKCTL0_TUPLE_MUXA(TRNGFCLKDIV_OFFSET, 0), /*!< TRNG Clk Divider. */