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Searched refs:TMR_CSCTRL_FAULT_MASK (Results 1 – 25 of 33) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MKM14ZA5/
DMKM14ZA5.h12077 #define TMR_CSCTRL_FAULT_MASK (0x2000U) macro
12083 … (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKM33ZA5/
DMKM33ZA5.h16782 #define TMR_CSCTRL_FAULT_MASK (0x2000U) macro
16788 … (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKM34ZA5/
DMKM34ZA5.h16778 #define TMR_CSCTRL_FAULT_MASK (0x2000U) macro
16784 … (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKM35Z7/
DMKM35Z7.h18198 #define TMR_CSCTRL_FAULT_MASK (0x2000U) macro
18204 … (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKM34Z7/
DMKM34Z7.h18332 #define TMR_CSCTRL_FAULT_MASK (0x2000U) macro
18338 …CTRL_FAULT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h31958 #define TMR_CSCTRL_FAULT_MASK (0x2000U) macro
31964 … (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h37237 #define TMR_CSCTRL_FAULT_MASK (0x2000U) macro
37243 … (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h37258 #define TMR_CSCTRL_FAULT_MASK (0x2000U) macro
37264 … (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h38796 #define TMR_CSCTRL_FAULT_MASK (0x2000U) macro
38802 … (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h40313 #define TMR_CSCTRL_FAULT_MASK (0x2000U) macro
40319 … (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h43062 #define TMR_CSCTRL_FAULT_MASK (0x2000U) macro
43068 … (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h43723 #define TMR_CSCTRL_FAULT_MASK (0x2000U) macro
43729 … (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h41197 #define TMR_CSCTRL_FAULT_MASK (0x2000U) macro
41203 … (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h45327 #define TMR_CSCTRL_FAULT_MASK (0x2000U) macro
45333 … (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h45391 #define TMR_CSCTRL_FAULT_MASK (0x2000U) macro
45397 … (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h74052 #define TMR_CSCTRL_FAULT_MASK (0x2000U) macro
74058 … (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)
DMIMXRT1175_cm7.h73150 #define TMR_CSCTRL_FAULT_MASK (0x2000U) macro
73156 … (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h72648 #define TMR_CSCTRL_FAULT_MASK (0x2000U) macro
72654 … (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)
DMIMXRT1165_cm4.h73550 #define TMR_CSCTRL_FAULT_MASK (0x2000U) macro
73556 … (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h73150 #define TMR_CSCTRL_FAULT_MASK (0x2000U) macro
73156 … (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm4.h79013 #define TMR_CSCTRL_FAULT_MASK (0x2000U) macro
79019 … (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)
DMIMXRT1166_cm7.h78111 #define TMR_CSCTRL_FAULT_MASK (0x2000U) macro
78117 … (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm4.h79512 #define TMR_CSCTRL_FAULT_MASK (0x2000U) macro
79518 … (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)
DMIMXRT1173_cm7.h78610 #define TMR_CSCTRL_FAULT_MASK (0x2000U) macro
78616 … (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/
DMIMXRT1172.h78613 #define TMR_CSCTRL_FAULT_MASK (0x2000U) macro
78619 … (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)

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