| /hal_nxp-latest/mcux/mcux-sdk/drivers/tmu_3/ |
| D | fsl_tmu.h | 205 base->TMR = ((base->TMR & ~TMU_TMR_MODE_MASK) | TMU_TMR_MODE(2)); in TMU_Enable()
209 base->TMR &= ~TMU_TMR_MODE_MASK; in TMU_Enable()
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| D | fsl_tmu.c | 126 base->TMR = TMU_TMR_ALPF(config->averageLPF); in TMU_Init()
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/tmu/ |
| D | fsl_tmu.h | 198 base->TMR |= TMU_TMR_ME_MASK; in TMU_Enable()
202 base->TMR &= ~TMU_TMR_ME_MASK; in TMU_Enable()
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| D | fsl_tmu.c | 169 base->TMR = TMU_TMR_ALPF(config->averageLPF) | TMU_TMR_MSITE(config->monitorSiteSelection); in TMU_Init()
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| /hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/ |
| D | S32K148_LPIT.h | 89 } TMR[LPIT_TMR_COUNT]; member
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| D | S32K118_LPIT.h | 89 } TMR[LPIT_TMR_COUNT]; member
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| D | S32K116_LPIT.h | 89 } TMR[LPIT_TMR_COUNT]; member
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| D | S32K142W_LPIT.h | 89 } TMR[LPIT_TMR_COUNT]; member
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| D | S32K146_LPIT.h | 89 } TMR[LPIT_TMR_COUNT]; member
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| D | S32K142_LPIT.h | 89 } TMR[LPIT_TMR_COUNT]; member
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| D | S32K144W_LPIT.h | 89 } TMR[LPIT_TMR_COUNT]; member
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| D | S32K144_LPIT.h | 89 } TMR[LPIT_TMR_COUNT]; member
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| D | S32K148_SAI.h | 91 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ member
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| /hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/ |
| D | S32Z2_TMU.h | 77 __IO uint32_t TMR; /**< Mode, offset: 0x0 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/sai/ |
| D | fsl_sai.c | 473 base->TMR = 0; in SAI_TxReset()
970 if (base->TMR == 0U) in SAI_TxSetFifoConfig()
1101 base->TMR = config->dataMaskedWord; in SAI_TxSetSerialDataConfig()
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| /hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/ |
| D | S32K344_SAI.h | 91 __IO uint32_t TMR; /**< Transmit Mask, offset: 0x60 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXC144/ |
| D | MCXC144.h | 3351 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXC143/ |
| D | MCXC143.h | 3351 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXC243/ |
| D | MCXC243.h | 3349 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXC244/ |
| D | MCXC244.h | 3351 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MK22F12810/ |
| D | MK22F12810.h | 5602 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXC444/ |
| D | MCXC444.h | 3351 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXC443/ |
| D | MCXC443.h | 3351 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKW22D5/ |
| D | MKW22D5.h | 4035 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKW24D5/ |
| D | MKW24D5.h | 4035 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ member
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