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Searched refs:SYSCON_WDT1CLKDIV_DIV_MASK (Results 1 – 16 of 16) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/drivers/
Dfsl_clock.c1349 ((SYSCON->WDT1CLKDIV & SYSCON_WDT1CLKDIV_DIV_MASK) + 1U)); in CLOCK_GetWdtClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/drivers/
Dfsl_clock.c1349 ((SYSCON->WDT1CLKDIV & SYSCON_WDT1CLKDIV_DIV_MASK) + 1U)); in CLOCK_GetWdtClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/drivers/
Dfsl_clock.c1751 ((SYSCON->WDT1CLKDIV & SYSCON_WDT1CLKDIV_DIV_MASK) + 1U)); in CLOCK_GetWdtClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/drivers/
Dfsl_clock.c1751 ((SYSCON->WDT1CLKDIV & SYSCON_WDT1CLKDIV_DIV_MASK) + 1U)); in CLOCK_GetWdtClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/drivers/
Dfsl_clock.c1751 ((SYSCON->WDT1CLKDIV & SYSCON_WDT1CLKDIV_DIV_MASK) + 1U)); in CLOCK_GetWdtClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/drivers/
Dfsl_clock.c1751 ((SYSCON->WDT1CLKDIV & SYSCON_WDT1CLKDIV_DIV_MASK) + 1U)); in CLOCK_GetWdtClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h57891 #define SYSCON_WDT1CLKDIV_DIV_MASK (0x3FU) macro
57894 … (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT1CLKDIV_DIV_SHIFT)) & SYSCON_WDT1CLKDIV_DIV_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h57849 #define SYSCON_WDT1CLKDIV_DIV_MASK (0x3FU) macro
57852 … (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT1CLKDIV_DIV_SHIFT)) & SYSCON_WDT1CLKDIV_DIV_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h73444 #define SYSCON_WDT1CLKDIV_DIV_MASK (0x3FU) macro
73447 … (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT1CLKDIV_DIV_SHIFT)) & SYSCON_WDT1CLKDIV_DIV_MASK)
DMCXN546_cm33_core1.h73444 #define SYSCON_WDT1CLKDIV_DIV_MASK (0x3FU) macro
73447 … (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT1CLKDIV_DIV_SHIFT)) & SYSCON_WDT1CLKDIV_DIV_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h73444 #define SYSCON_WDT1CLKDIV_DIV_MASK (0x3FU) macro
73447 … (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT1CLKDIV_DIV_SHIFT)) & SYSCON_WDT1CLKDIV_DIV_MASK)
DMCXN547_cm33_core1.h73444 #define SYSCON_WDT1CLKDIV_DIV_MASK (0x3FU) macro
73447 … (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT1CLKDIV_DIV_SHIFT)) & SYSCON_WDT1CLKDIV_DIV_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h76110 #define SYSCON_WDT1CLKDIV_DIV_MASK (0x3FU) macro
76113 … (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT1CLKDIV_DIV_SHIFT)) & SYSCON_WDT1CLKDIV_DIV_MASK)
DMCXN947_cm33_core0.h76110 #define SYSCON_WDT1CLKDIV_DIV_MASK (0x3FU) macro
76113 … (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT1CLKDIV_DIV_SHIFT)) & SYSCON_WDT1CLKDIV_DIV_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h76110 #define SYSCON_WDT1CLKDIV_DIV_MASK (0x3FU) macro
76113 … (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT1CLKDIV_DIV_SHIFT)) & SYSCON_WDT1CLKDIV_DIV_MASK)
DMCXN946_cm33_core1.h76110 #define SYSCON_WDT1CLKDIV_DIV_MASK (0x3FU) macro
76113 … (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT1CLKDIV_DIV_SHIFT)) & SYSCON_WDT1CLKDIV_DIV_MASK)