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Searched refs:SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK (Results 1 – 13 of 13) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h47181 #define SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK (0xFFFFFFFFU) macro
47187 …t)(((uint32_t)(x)) << SYSCON_SWD_ACCESS_CPU_SEC_CODE_SHIFT)) & SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5534/
DLPC5534.h47181 #define SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK (0xFFFFFFFFU) macro
47187 …t)(((uint32_t)(x)) << SYSCON_SWD_ACCESS_CPU_SEC_CODE_SHIFT)) & SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S36/
DLPC55S36.h56886 #define SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK (0xFFFFFFFFU) macro
56892 …t)(((uint32_t)(x)) << SYSCON_SWD_ACCESS_CPU_SEC_CODE_SHIFT)) & SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h59819 #define SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK (0xFFFFFFFFU) macro
59825 …t)(((uint32_t)(x)) << SYSCON_SWD_ACCESS_CPU_SEC_CODE_SHIFT)) & SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h59777 #define SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK (0xFFFFFFFFU) macro
59783 …t)(((uint32_t)(x)) << SYSCON_SWD_ACCESS_CPU_SEC_CODE_SHIFT)) & SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h75932 #define SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK (0xFFFFFFFFU) macro
75938 …t)(((uint32_t)(x)) << SYSCON_SWD_ACCESS_CPU_SEC_CODE_SHIFT)) & SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK)
DMCXN546_cm33_core1.h75932 #define SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK (0xFFFFFFFFU) macro
75938 …t)(((uint32_t)(x)) << SYSCON_SWD_ACCESS_CPU_SEC_CODE_SHIFT)) & SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h75932 #define SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK (0xFFFFFFFFU) macro
75938 …t)(((uint32_t)(x)) << SYSCON_SWD_ACCESS_CPU_SEC_CODE_SHIFT)) & SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK)
DMCXN547_cm33_core1.h75932 #define SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK (0xFFFFFFFFU) macro
75938 …t)(((uint32_t)(x)) << SYSCON_SWD_ACCESS_CPU_SEC_CODE_SHIFT)) & SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h78598 #define SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK (0xFFFFFFFFU) macro
78604 …t)(((uint32_t)(x)) << SYSCON_SWD_ACCESS_CPU_SEC_CODE_SHIFT)) & SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK)
DMCXN947_cm33_core0.h78598 #define SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK (0xFFFFFFFFU) macro
78604 …t)(((uint32_t)(x)) << SYSCON_SWD_ACCESS_CPU_SEC_CODE_SHIFT)) & SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h78598 #define SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK (0xFFFFFFFFU) macro
78604 …t)(((uint32_t)(x)) << SYSCON_SWD_ACCESS_CPU_SEC_CODE_SHIFT)) & SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK)
DMCXN946_cm33_core1.h78598 #define SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK (0xFFFFFFFFU) macro
78604 …t)(((uint32_t)(x)) << SYSCON_SWD_ACCESS_CPU_SEC_CODE_SHIFT)) & SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK)