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Searched refs:SYSCON_I3C0FCLKSTCDIV_DIV_MASK (Results 1 – 12 of 12) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/drivers/
Dfsl_clock.c1436 div = ((id == 0U) ? ((SYSCON->I3C0FCLKSTCDIV & SYSCON_I3C0FCLKSTCDIV_DIV_MASK) + 1U) : in CLOCK_GetI3cSTCClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/drivers/
Dfsl_clock.c1436 div = ((id == 0U) ? ((SYSCON->I3C0FCLKSTCDIV & SYSCON_I3C0FCLKSTCDIV_DIV_MASK) + 1U) : in CLOCK_GetI3cSTCClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/drivers/
Dfsl_clock.c1436 div = ((id == 0U) ? ((SYSCON->I3C0FCLKSTCDIV & SYSCON_I3C0FCLKSTCDIV_DIV_MASK) + 1U) : in CLOCK_GetI3cSTCClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/drivers/
Dfsl_clock.c1436 div = ((id == 0U) ? ((SYSCON->I3C0FCLKSTCDIV & SYSCON_I3C0FCLKSTCDIV_DIV_MASK) + 1U) : in CLOCK_GetI3cSTCClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h72904 #define SYSCON_I3C0FCLKSTCDIV_DIV_MASK (0xFFU) macro
72907 …(((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKSTCDIV_DIV_SHIFT)) & SYSCON_I3C0FCLKSTCDIV_DIV_MASK)
DMCXN546_cm33_core1.h72904 #define SYSCON_I3C0FCLKSTCDIV_DIV_MASK (0xFFU) macro
72907 …(((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKSTCDIV_DIV_SHIFT)) & SYSCON_I3C0FCLKSTCDIV_DIV_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h72904 #define SYSCON_I3C0FCLKSTCDIV_DIV_MASK (0xFFU) macro
72907 …(((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKSTCDIV_DIV_SHIFT)) & SYSCON_I3C0FCLKSTCDIV_DIV_MASK)
DMCXN547_cm33_core1.h72904 #define SYSCON_I3C0FCLKSTCDIV_DIV_MASK (0xFFU) macro
72907 …(((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKSTCDIV_DIV_SHIFT)) & SYSCON_I3C0FCLKSTCDIV_DIV_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h75570 #define SYSCON_I3C0FCLKSTCDIV_DIV_MASK (0xFFU) macro
75573 …(((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKSTCDIV_DIV_SHIFT)) & SYSCON_I3C0FCLKSTCDIV_DIV_MASK)
DMCXN947_cm33_core0.h75570 #define SYSCON_I3C0FCLKSTCDIV_DIV_MASK (0xFFU) macro
75573 …(((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKSTCDIV_DIV_SHIFT)) & SYSCON_I3C0FCLKSTCDIV_DIV_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h75570 #define SYSCON_I3C0FCLKSTCDIV_DIV_MASK (0xFFU) macro
75573 …(((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKSTCDIV_DIV_SHIFT)) & SYSCON_I3C0FCLKSTCDIV_DIV_MASK)
DMCXN946_cm33_core1.h75570 #define SYSCON_I3C0FCLKSTCDIV_DIV_MASK (0xFFU) macro
75573 …(((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKSTCDIV_DIV_SHIFT)) & SYSCON_I3C0FCLKSTCDIV_DIV_MASK)