Home
last modified time | relevance | path

Searched refs:SYSCON_I3C0FCLKDIV_DIV_MASK (Results 1 – 16 of 16) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/drivers/
Dfsl_clock.c1171 div = ((id == 0U) ? ((SYSCON->I3C0FCLKDIV & SYSCON_I3C0FCLKDIV_DIV_MASK) + 1U) : in CLOCK_GetI3cClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/drivers/
Dfsl_clock.c1171 div = ((id == 0U) ? ((SYSCON->I3C0FCLKDIV & SYSCON_I3C0FCLKDIV_DIV_MASK) + 1U) : in CLOCK_GetI3cClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/drivers/
Dfsl_clock.c1389 div = ((id == 0U) ? ((SYSCON->I3C0FCLKDIV & SYSCON_I3C0FCLKDIV_DIV_MASK) + 1U) : in CLOCK_GetI3cClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/drivers/
Dfsl_clock.c1389 div = ((id == 0U) ? ((SYSCON->I3C0FCLKDIV & SYSCON_I3C0FCLKDIV_DIV_MASK) + 1U) : in CLOCK_GetI3cClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/drivers/
Dfsl_clock.c1389 div = ((id == 0U) ? ((SYSCON->I3C0FCLKDIV & SYSCON_I3C0FCLKDIV_DIV_MASK) + 1U) : in CLOCK_GetI3cClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/drivers/
Dfsl_clock.c1389 div = ((id == 0U) ? ((SYSCON->I3C0FCLKDIV & SYSCON_I3C0FCLKDIV_DIV_MASK) + 1U) : in CLOCK_GetI3cClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h57620 #define SYSCON_I3C0FCLKDIV_DIV_MASK (0xFFU) macro
57623 … (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKDIV_DIV_SHIFT)) & SYSCON_I3C0FCLKDIV_DIV_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h57578 #define SYSCON_I3C0FCLKDIV_DIV_MASK (0xFFU) macro
57581 … (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKDIV_DIV_SHIFT)) & SYSCON_I3C0FCLKDIV_DIV_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h72970 #define SYSCON_I3C0FCLKDIV_DIV_MASK (0xFFU) macro
72973 … (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKDIV_DIV_SHIFT)) & SYSCON_I3C0FCLKDIV_DIV_MASK)
DMCXN546_cm33_core1.h72970 #define SYSCON_I3C0FCLKDIV_DIV_MASK (0xFFU) macro
72973 … (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKDIV_DIV_SHIFT)) & SYSCON_I3C0FCLKDIV_DIV_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h72970 #define SYSCON_I3C0FCLKDIV_DIV_MASK (0xFFU) macro
72973 … (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKDIV_DIV_SHIFT)) & SYSCON_I3C0FCLKDIV_DIV_MASK)
DMCXN547_cm33_core1.h72970 #define SYSCON_I3C0FCLKDIV_DIV_MASK (0xFFU) macro
72973 … (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKDIV_DIV_SHIFT)) & SYSCON_I3C0FCLKDIV_DIV_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h75636 #define SYSCON_I3C0FCLKDIV_DIV_MASK (0xFFU) macro
75639 … (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKDIV_DIV_SHIFT)) & SYSCON_I3C0FCLKDIV_DIV_MASK)
DMCXN947_cm33_core0.h75636 #define SYSCON_I3C0FCLKDIV_DIV_MASK (0xFFU) macro
75639 … (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKDIV_DIV_SHIFT)) & SYSCON_I3C0FCLKDIV_DIV_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h75636 #define SYSCON_I3C0FCLKDIV_DIV_MASK (0xFFU) macro
75639 … (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKDIV_DIV_SHIFT)) & SYSCON_I3C0FCLKDIV_DIV_MASK)
DMCXN946_cm33_core1.h75636 #define SYSCON_I3C0FCLKDIV_DIV_MASK (0xFFU) macro
75639 … (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKDIV_DIV_SHIFT)) & SYSCON_I3C0FCLKDIV_DIV_MASK)