Home
last modified time | relevance | path

Searched refs:SYSCON_EMVSIM1CLKDIV_DIV_MASK (Results 1 – 12 of 12) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/drivers/
Dfsl_clock.c1991 ((SYSCON->EMVSIM1CLKDIV & SYSCON_EMVSIM1CLKDIV_DIV_MASK) + 1U)); in CLOCK_GetEmvsimClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/drivers/
Dfsl_clock.c1991 ((SYSCON->EMVSIM1CLKDIV & SYSCON_EMVSIM1CLKDIV_DIV_MASK) + 1U)); in CLOCK_GetEmvsimClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/drivers/
Dfsl_clock.c1991 ((SYSCON->EMVSIM1CLKDIV & SYSCON_EMVSIM1CLKDIV_DIV_MASK) + 1U)); in CLOCK_GetEmvsimClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/drivers/
Dfsl_clock.c1991 ((SYSCON->EMVSIM1CLKDIV & SYSCON_EMVSIM1CLKDIV_DIV_MASK) + 1U)); in CLOCK_GetEmvsimClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h74158 #define SYSCON_EMVSIM1CLKDIV_DIV_MASK (0x7U) macro
74161 … (((uint32_t)(((uint32_t)(x)) << SYSCON_EMVSIM1CLKDIV_DIV_SHIFT)) & SYSCON_EMVSIM1CLKDIV_DIV_MASK)
DMCXN546_cm33_core1.h74158 #define SYSCON_EMVSIM1CLKDIV_DIV_MASK (0x7U) macro
74161 … (((uint32_t)(((uint32_t)(x)) << SYSCON_EMVSIM1CLKDIV_DIV_SHIFT)) & SYSCON_EMVSIM1CLKDIV_DIV_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h74158 #define SYSCON_EMVSIM1CLKDIV_DIV_MASK (0x7U) macro
74161 … (((uint32_t)(((uint32_t)(x)) << SYSCON_EMVSIM1CLKDIV_DIV_SHIFT)) & SYSCON_EMVSIM1CLKDIV_DIV_MASK)
DMCXN547_cm33_core1.h74158 #define SYSCON_EMVSIM1CLKDIV_DIV_MASK (0x7U) macro
74161 … (((uint32_t)(((uint32_t)(x)) << SYSCON_EMVSIM1CLKDIV_DIV_SHIFT)) & SYSCON_EMVSIM1CLKDIV_DIV_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h76824 #define SYSCON_EMVSIM1CLKDIV_DIV_MASK (0x7U) macro
76827 … (((uint32_t)(((uint32_t)(x)) << SYSCON_EMVSIM1CLKDIV_DIV_SHIFT)) & SYSCON_EMVSIM1CLKDIV_DIV_MASK)
DMCXN947_cm33_core0.h76824 #define SYSCON_EMVSIM1CLKDIV_DIV_MASK (0x7U) macro
76827 … (((uint32_t)(((uint32_t)(x)) << SYSCON_EMVSIM1CLKDIV_DIV_SHIFT)) & SYSCON_EMVSIM1CLKDIV_DIV_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h76824 #define SYSCON_EMVSIM1CLKDIV_DIV_MASK (0x7U) macro
76827 … (((uint32_t)(((uint32_t)(x)) << SYSCON_EMVSIM1CLKDIV_DIV_SHIFT)) & SYSCON_EMVSIM1CLKDIV_DIV_MASK)
DMCXN946_cm33_core1.h76824 #define SYSCON_EMVSIM1CLKDIV_DIV_MASK (0x7U) macro
76827 … (((uint32_t)(((uint32_t)(x)) << SYSCON_EMVSIM1CLKDIV_DIV_SHIFT)) & SYSCON_EMVSIM1CLKDIV_DIV_MASK)