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Searched refs:SYSCON_CMP1RRCLKDIV_RESET_MASK (Results 1 – 10 of 10) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h58114 #define SYSCON_CMP1RRCLKDIV_RESET_MASK (0x20000000U) macro
58120 …(((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1RRCLKDIV_RESET_SHIFT)) & SYSCON_CMP1RRCLKDIV_RESET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h58072 #define SYSCON_CMP1RRCLKDIV_RESET_MASK (0x20000000U) macro
58078 …(((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1RRCLKDIV_RESET_SHIFT)) & SYSCON_CMP1RRCLKDIV_RESET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h73667 #define SYSCON_CMP1RRCLKDIV_RESET_MASK (0x20000000U) macro
73673 …(((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1RRCLKDIV_RESET_SHIFT)) & SYSCON_CMP1RRCLKDIV_RESET_MASK)
DMCXN546_cm33_core1.h73667 #define SYSCON_CMP1RRCLKDIV_RESET_MASK (0x20000000U) macro
73673 …(((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1RRCLKDIV_RESET_SHIFT)) & SYSCON_CMP1RRCLKDIV_RESET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h73667 #define SYSCON_CMP1RRCLKDIV_RESET_MASK (0x20000000U) macro
73673 …(((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1RRCLKDIV_RESET_SHIFT)) & SYSCON_CMP1RRCLKDIV_RESET_MASK)
DMCXN547_cm33_core1.h73667 #define SYSCON_CMP1RRCLKDIV_RESET_MASK (0x20000000U) macro
73673 …(((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1RRCLKDIV_RESET_SHIFT)) & SYSCON_CMP1RRCLKDIV_RESET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h76333 #define SYSCON_CMP1RRCLKDIV_RESET_MASK (0x20000000U) macro
76339 …(((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1RRCLKDIV_RESET_SHIFT)) & SYSCON_CMP1RRCLKDIV_RESET_MASK)
DMCXN947_cm33_core0.h76333 #define SYSCON_CMP1RRCLKDIV_RESET_MASK (0x20000000U) macro
76339 …(((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1RRCLKDIV_RESET_SHIFT)) & SYSCON_CMP1RRCLKDIV_RESET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h76333 #define SYSCON_CMP1RRCLKDIV_RESET_MASK (0x20000000U) macro
76339 …(((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1RRCLKDIV_RESET_SHIFT)) & SYSCON_CMP1RRCLKDIV_RESET_MASK)
DMCXN946_cm33_core1.h76333 #define SYSCON_CMP1RRCLKDIV_RESET_MASK (0x20000000U) macro
76339 …(((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1RRCLKDIV_RESET_SHIFT)) & SYSCON_CMP1RRCLKDIV_RESET_MASK)