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Searched refs:SYSCON_CMP0RRCLKDIV_RESET_MASK (Results 1 – 10 of 10) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h58012 #define SYSCON_CMP0RRCLKDIV_RESET_MASK (0x20000000U) macro
58018 …(((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0RRCLKDIV_RESET_SHIFT)) & SYSCON_CMP0RRCLKDIV_RESET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h57970 #define SYSCON_CMP0RRCLKDIV_RESET_MASK (0x20000000U) macro
57976 …(((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0RRCLKDIV_RESET_SHIFT)) & SYSCON_CMP0RRCLKDIV_RESET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h73565 #define SYSCON_CMP0RRCLKDIV_RESET_MASK (0x20000000U) macro
73571 …(((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0RRCLKDIV_RESET_SHIFT)) & SYSCON_CMP0RRCLKDIV_RESET_MASK)
DMCXN546_cm33_core1.h73565 #define SYSCON_CMP0RRCLKDIV_RESET_MASK (0x20000000U) macro
73571 …(((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0RRCLKDIV_RESET_SHIFT)) & SYSCON_CMP0RRCLKDIV_RESET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h73565 #define SYSCON_CMP0RRCLKDIV_RESET_MASK (0x20000000U) macro
73571 …(((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0RRCLKDIV_RESET_SHIFT)) & SYSCON_CMP0RRCLKDIV_RESET_MASK)
DMCXN547_cm33_core1.h73565 #define SYSCON_CMP0RRCLKDIV_RESET_MASK (0x20000000U) macro
73571 …(((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0RRCLKDIV_RESET_SHIFT)) & SYSCON_CMP0RRCLKDIV_RESET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h76231 #define SYSCON_CMP0RRCLKDIV_RESET_MASK (0x20000000U) macro
76237 …(((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0RRCLKDIV_RESET_SHIFT)) & SYSCON_CMP0RRCLKDIV_RESET_MASK)
DMCXN947_cm33_core0.h76231 #define SYSCON_CMP0RRCLKDIV_RESET_MASK (0x20000000U) macro
76237 …(((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0RRCLKDIV_RESET_SHIFT)) & SYSCON_CMP0RRCLKDIV_RESET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h76231 #define SYSCON_CMP0RRCLKDIV_RESET_MASK (0x20000000U) macro
76237 …(((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0RRCLKDIV_RESET_SHIFT)) & SYSCON_CMP0RRCLKDIV_RESET_MASK)
DMCXN946_cm33_core1.h76231 #define SYSCON_CMP0RRCLKDIV_RESET_MASK (0x20000000U) macro
76237 …(((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0RRCLKDIV_RESET_SHIFT)) & SYSCON_CMP0RRCLKDIV_RESET_MASK)