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Searched refs:SYSCON_AHBCLKCTRL0_RAMC_CTRL_MASK (Results 1 – 10 of 10) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h56075 #define SYSCON_AHBCLKCTRL0_RAMC_CTRL_MASK (0x8U) macro
56081 …t32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RAMC_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL0_RAMC_CTRL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h56033 #define SYSCON_AHBCLKCTRL0_RAMC_CTRL_MASK (0x8U) macro
56039 …t32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RAMC_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL0_RAMC_CTRL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h70780 #define SYSCON_AHBCLKCTRL0_RAMC_CTRL_MASK (0x8U) macro
70786 …t32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RAMC_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL0_RAMC_CTRL_MASK)
DMCXN546_cm33_core1.h70780 #define SYSCON_AHBCLKCTRL0_RAMC_CTRL_MASK (0x8U) macro
70786 …t32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RAMC_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL0_RAMC_CTRL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h70780 #define SYSCON_AHBCLKCTRL0_RAMC_CTRL_MASK (0x8U) macro
70786 …t32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RAMC_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL0_RAMC_CTRL_MASK)
DMCXN547_cm33_core1.h70780 #define SYSCON_AHBCLKCTRL0_RAMC_CTRL_MASK (0x8U) macro
70786 …t32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RAMC_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL0_RAMC_CTRL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h73446 #define SYSCON_AHBCLKCTRL0_RAMC_CTRL_MASK (0x8U) macro
73452 …t32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RAMC_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL0_RAMC_CTRL_MASK)
DMCXN947_cm33_core0.h73446 #define SYSCON_AHBCLKCTRL0_RAMC_CTRL_MASK (0x8U) macro
73452 …t32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RAMC_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL0_RAMC_CTRL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h73446 #define SYSCON_AHBCLKCTRL0_RAMC_CTRL_MASK (0x8U) macro
73452 …t32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RAMC_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL0_RAMC_CTRL_MASK)
DMCXN946_cm33_core1.h73446 #define SYSCON_AHBCLKCTRL0_RAMC_CTRL_MASK (0x8U) macro
73452 …t32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RAMC_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL0_RAMC_CTRL_MASK)