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Searched refs:STATUS (Results 1 – 25 of 304) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/hashcrypt/
Dfsl_hashcrypt.c289 while ((wait > 0U) && (base->STATUS == 0U)) in hashcrypt_check_need_key()
294 if (0U == (base->STATUS & HASHCRYPT_STATUS_NEEDKEY_MASK)) in hashcrypt_check_need_key()
323 while ((0U == (base->STATUS & HASHCRYPT_STATUS_DIGEST_MASK)) && in hashcrypt_get_data()
324 (0U == (base->STATUS & HASHCRYPT_STATUS_ERROR_MASK))) in hashcrypt_get_data()
328 if (0U == (base->STATUS & HASHCRYPT_STATUS_ERROR_MASK)) in hashcrypt_get_data()
435 while ((0U == (base->STATUS & HASHCRYPT_STATUS_DIGEST_MASK)) && in hashcrypt_aes_one_block_aligned()
436 (0U == (base->STATUS & HASHCRYPT_STATUS_ERROR_MASK))) in hashcrypt_aes_one_block_aligned()
449 if (0U == (base->STATUS & HASHCRYPT_STATUS_ERROR_MASK)) in hashcrypt_aes_one_block_aligned()
492 while ((0U == (base->STATUS & HASHCRYPT_STATUS_DIGEST_MASK)) && in hashcrypt_aes_one_block_unaligned()
493 (0U == (base->STATUS & HASHCRYPT_STATUS_ERROR_MASK))) in hashcrypt_aes_one_block_unaligned()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/drivers/pmc0/
Dfsl_pmc0.h339 while ((PMC0->STATUS & PMC0_STATUS_COREVLF_MASK) == PMC0_STATUS_COREVLF_MASK) in PMC0_ConfigureHsrunMode()
346 while ((PMC0->STATUS & PMC0_STATUS_COREVLF_MASK) == PMC0_STATUS_COREVLF_MASK) in PMC0_ConfigureHsrunMode()
370 while ((PMC0->STATUS & PMC0_STATUS_COREVLF_MASK) == PMC0_STATUS_COREVLF_MASK) in PMC0_ConfigureRunMode()
377 while ((PMC0->STATUS & PMC0_STATUS_COREVLF_MASK) == PMC0_STATUS_COREVLF_MASK) in PMC0_ConfigureRunMode()
589 return PMC0->STATUS; in PMC0_GetStatusFlags()
820 while ((PMC0->STATUS & PMC0_STATUS_SRAMF_MASK) == PMC0_STATUS_SRAMF_MASK) in PMC0_ConfigureSramBankPowerDown()
827 while ((PMC0->STATUS & PMC0_STATUS_SRAMF_MASK) == PMC0_STATUS_SRAMF_MASK) in PMC0_ConfigureSramBankPowerDown()
/hal_nxp-latest/mcux/mcux-sdk/drivers/irtc/
Dfsl_irtc.c450 …while ((0U != (base->STATUS & (uint16_t)RTC_STATUS_WRITE_PROT_EN_MASK)) && (0U != repeatProtectSeq… in IRTC_SetWriteProtection()
453 *(__IO uint8_t *)(&base->STATUS) = 0U; in IRTC_SetWriteProtection()
454 *(__IO uint8_t *)(&base->STATUS) = 0x40U; in IRTC_SetWriteProtection()
455 *(__IO uint8_t *)(&base->STATUS) = 0xC0U; in IRTC_SetWriteProtection()
456 *(__IO uint8_t *)(&base->STATUS) = 0x80U; in IRTC_SetWriteProtection()
463 …while ((0U == ((base->STATUS & (uint16_t)RTC_STATUS_WRITE_PROT_EN_MASK) >> RTC_STATUS_WRITE_PROT_E… in IRTC_SetWriteProtection()
466 *(__IO uint8_t *)(&base->STATUS) = 0x80U; in IRTC_SetWriteProtection()
Dfsl_irtc.h433 return (base->ISR | ((uint32_t)base->STATUS << 16U) | ((uint32_t)base->WAKE_TIMER_CTRL << 28U)); in IRTC_GetStatusFlags()
435 return (base->ISR | ((uint32_t)base->STATUS << 16U)); in IRTC_GetStatusFlags()
449 base->STATUS = (base->STATUS & ~IRTC_STATUS_W1C_BITS) | in IRTC_ClearStatusFlags()
/hal_nxp-latest/mcux/mcux-sdk/drivers/itrc/
Dfsl_itrc.c66 base->STATUS |= word; in ITRC_ClearStatus()
81 return base->STATUS; in ITRC_GetStatus()
133 base->STATUS |= (IN_0_15_EVENTS_MASK | OUT_ACTIONS_MASK); in ITRC_ClearAllStatus()
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5534/drivers/
Dfsl_power.c525 … pmc_reg_data = PMC->STATUS & (PMC_STATUS_FSMDCDCENABLE_MASK | PMC_STATUS_FSMLDOCOREHPENABLE_MASK | in POWER_SetCorePowerSource()
557 … pmc_reg_data = PMC->STATUS & (PMC_STATUS_FSMDCDCENABLE_MASK | PMC_STATUS_FSMLDOCOREHPENABLE_MASK | in POWER_SetCorePowerSource()
579 … pmc_reg_data = PMC->STATUS & (PMC_STATUS_FSMDCDCENABLE_MASK | PMC_STATUS_FSMLDOCOREHPENABLE_MASK | in POWER_SetCorePowerSource()
601 … pmc_reg_data = PMC->STATUS & (PMC_STATUS_FSMDCDCENABLE_MASK | PMC_STATUS_FSMLDOCOREHPENABLE_MASK | in POWER_SetCorePowerSource()
628 reg_status = PMC->STATUS; in POWER_GetCorePowerSource()
680 if ((PMC->STATUS & PMC_STATUS_FSMDCDCENABLE_MASK) == 0UL) in POWER_CorePowerSourceControl()
692 if ((PMC->STATUS & PMC_STATUS_FSMDCDCENABLE_MASK) != 0UL) in POWER_CorePowerSourceControl()
719 if ((PMC->STATUS & PMC_STATUS_FSMLDOCOREHPENABLE_MASK) == 0UL) in POWER_CorePowerSourceControl()
731 if ((PMC->STATUS & PMC_STATUS_FSMLDOCOREHPENABLE_MASK) != 0UL) in POWER_CorePowerSourceControl()
748 …if ((PMC->STATUS & (PMC_STATUS_FSMLDOCORELPENABLE_MASK | PMC_STATUS_FSMLDOCOREEXPTMRENABLE_MASK)) … in POWER_CorePowerSourceControl()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5536/drivers/
Dfsl_power.c525 … pmc_reg_data = PMC->STATUS & (PMC_STATUS_FSMDCDCENABLE_MASK | PMC_STATUS_FSMLDOCOREHPENABLE_MASK | in POWER_SetCorePowerSource()
557 … pmc_reg_data = PMC->STATUS & (PMC_STATUS_FSMDCDCENABLE_MASK | PMC_STATUS_FSMLDOCOREHPENABLE_MASK | in POWER_SetCorePowerSource()
579 … pmc_reg_data = PMC->STATUS & (PMC_STATUS_FSMDCDCENABLE_MASK | PMC_STATUS_FSMLDOCOREHPENABLE_MASK | in POWER_SetCorePowerSource()
601 … pmc_reg_data = PMC->STATUS & (PMC_STATUS_FSMDCDCENABLE_MASK | PMC_STATUS_FSMLDOCOREHPENABLE_MASK | in POWER_SetCorePowerSource()
628 reg_status = PMC->STATUS; in POWER_GetCorePowerSource()
680 if ((PMC->STATUS & PMC_STATUS_FSMDCDCENABLE_MASK) == 0UL) in POWER_CorePowerSourceControl()
692 if ((PMC->STATUS & PMC_STATUS_FSMDCDCENABLE_MASK) != 0UL) in POWER_CorePowerSourceControl()
719 if ((PMC->STATUS & PMC_STATUS_FSMLDOCOREHPENABLE_MASK) == 0UL) in POWER_CorePowerSourceControl()
731 if ((PMC->STATUS & PMC_STATUS_FSMLDOCOREHPENABLE_MASK) != 0UL) in POWER_CorePowerSourceControl()
748 …if ((PMC->STATUS & (PMC_STATUS_FSMLDOCORELPENABLE_MASK | PMC_STATUS_FSMLDOCOREEXPTMRENABLE_MASK)) … in POWER_CorePowerSourceControl()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S36/drivers/
Dfsl_power.c525 … pmc_reg_data = PMC->STATUS & (PMC_STATUS_FSMDCDCENABLE_MASK | PMC_STATUS_FSMLDOCOREHPENABLE_MASK | in POWER_SetCorePowerSource()
557 … pmc_reg_data = PMC->STATUS & (PMC_STATUS_FSMDCDCENABLE_MASK | PMC_STATUS_FSMLDOCOREHPENABLE_MASK | in POWER_SetCorePowerSource()
579 … pmc_reg_data = PMC->STATUS & (PMC_STATUS_FSMDCDCENABLE_MASK | PMC_STATUS_FSMLDOCOREHPENABLE_MASK | in POWER_SetCorePowerSource()
601 … pmc_reg_data = PMC->STATUS & (PMC_STATUS_FSMDCDCENABLE_MASK | PMC_STATUS_FSMLDOCOREHPENABLE_MASK | in POWER_SetCorePowerSource()
628 reg_status = PMC->STATUS; in POWER_GetCorePowerSource()
680 if ((PMC->STATUS & PMC_STATUS_FSMDCDCENABLE_MASK) == 0UL) in POWER_CorePowerSourceControl()
692 if ((PMC->STATUS & PMC_STATUS_FSMDCDCENABLE_MASK) != 0UL) in POWER_CorePowerSourceControl()
719 if ((PMC->STATUS & PMC_STATUS_FSMLDOCOREHPENABLE_MASK) == 0UL) in POWER_CorePowerSourceControl()
731 if ((PMC->STATUS & PMC_STATUS_FSMLDOCOREHPENABLE_MASK) != 0UL) in POWER_CorePowerSourceControl()
748 …if ((PMC->STATUS & (PMC_STATUS_FSMLDOCORELPENABLE_MASK | PMC_STATUS_FSMLDOCOREEXPTMRENABLE_MASK)) … in POWER_CorePowerSourceControl()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/drivers/sha/
Dfsl_sha.c278 while (0U == (base->STATUS & SHA_STATUS_WAITING_MASK)) in sha_one_block()
374 while (0U == (base->STATUS & SHA_STATUS_WAITING_MASK)) in sha_process_message_data_master()
396 while (0U == (base->STATUS & SHA_STATUS_DIGEST_MASK)) in sha_process_message_data_master()
457 while (0U == (base->STATUS & SHA_STATUS_DIGEST_MASK)) in sha_finalize()
798 if (0U == (base->STATUS & SHA_STATUS_ERROR_MASK)) in SHA_DriverIRQHandler()
/hal_nxp-latest/mcux/mcux-sdk/drivers/sdif/
Dfsl_sdif.h584 …return (base->STATUS & SDIF_STATUS_DATA_3_STATUS_MASK) == SDIF_STATUS_DATA_3_STATUS_MASK ? 1UL : 0… in SDIF_DetectCardInsert()
603 …return (base->STATUS & SDIF_STATUS_DATA_3_STATUS_MASK) == SDIF_STATUS_DATA_3_STATUS_MASK ? 1UL : 0… in SDIF_DetectCard1Insert()
684 …return (base->STATUS & SDIF_STATUS_DATA_3_STATUS_MASK) == SDIF_STATUS_DATA_3_STATUS_MASK ? 1UL : 0… in SDIF_DetectCardInsert()
997 return base->STATUS; in SDIF_GetControllerStatus()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/drivers/
Dfsl_power.c214 while ((PMC->STATUS & PMC_STATUS_BUSY_MASK) != 0U) in POWER_ApplyPD()
219 while ((PMC->STATUS & PMC_STATUS_BUSY_MASK) != 0U) in POWER_ApplyPD()
1146 while ((PMC->STATUS & PMC_STATUS_BUSY_MASK) != 0U) /* Cannot set APPLYCFG when ACTIVEFSM is 1 */ in AT_QUICKACCESS_SECTION_CODE()
1150 …while ((PMC->STATUS & PMC_STATUS_BUSY_MASK) != 0U) /* Wait all PMC finite state machines finished.… in AT_QUICKACCESS_SECTION_CODE()
1186 if ((PMC->STATUS & PMC_STATUS_DSSENS_MASK) == 0U) in AT_QUICKACCESS_SECTION_CODE()
1402 while ((PMC->STATUS & PMC_STATUS_BUSY_MASK) != 0U) /* Cannot set APPLYCFG when ACTIVEFSM is 1 */ in AT_QUICKACCESS_SECTION_CODE()
1406 …while ((PMC->STATUS & PMC_STATUS_BUSY_MASK) != 0U) /* Wait all PMC finite state machines finished.… in AT_QUICKACCESS_SECTION_CODE()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/drivers/
Dfsl_power.c214 while ((PMC->STATUS & PMC_STATUS_BUSY_MASK) != 0U) in POWER_ApplyPD()
219 while ((PMC->STATUS & PMC_STATUS_BUSY_MASK) != 0U) in POWER_ApplyPD()
1146 while ((PMC->STATUS & PMC_STATUS_BUSY_MASK) != 0U) /* Cannot set APPLYCFG when ACTIVEFSM is 1 */ in AT_QUICKACCESS_SECTION_CODE()
1150 …while ((PMC->STATUS & PMC_STATUS_BUSY_MASK) != 0U) /* Wait all PMC finite state machines finished.… in AT_QUICKACCESS_SECTION_CODE()
1186 if ((PMC->STATUS & PMC_STATUS_DSSENS_MASK) == 0U) in AT_QUICKACCESS_SECTION_CODE()
1402 while ((PMC->STATUS & PMC_STATUS_BUSY_MASK) != 0U) /* Cannot set APPLYCFG when ACTIVEFSM is 1 */ in AT_QUICKACCESS_SECTION_CODE()
1406 …while ((PMC->STATUS & PMC_STATUS_BUSY_MASK) != 0U) /* Wait all PMC finite state machines finished.… in AT_QUICKACCESS_SECTION_CODE()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/drivers/
Dfsl_power.c214 while ((PMC->STATUS & PMC_STATUS_BUSY_MASK) != 0U) in POWER_ApplyPD()
219 while ((PMC->STATUS & PMC_STATUS_BUSY_MASK) != 0U) in POWER_ApplyPD()
1146 while ((PMC->STATUS & PMC_STATUS_BUSY_MASK) != 0U) /* Cannot set APPLYCFG when ACTIVEFSM is 1 */ in AT_QUICKACCESS_SECTION_CODE()
1150 …while ((PMC->STATUS & PMC_STATUS_BUSY_MASK) != 0U) /* Wait all PMC finite state machines finished.… in AT_QUICKACCESS_SECTION_CODE()
1186 if ((PMC->STATUS & PMC_STATUS_DSSENS_MASK) == 0U) in AT_QUICKACCESS_SECTION_CODE()
1402 while ((PMC->STATUS & PMC_STATUS_BUSY_MASK) != 0U) /* Cannot set APPLYCFG when ACTIVEFSM is 1 */ in AT_QUICKACCESS_SECTION_CODE()
1406 …while ((PMC->STATUS & PMC_STATUS_BUSY_MASK) != 0U) /* Wait all PMC finite state machines finished.… in AT_QUICKACCESS_SECTION_CODE()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/drivers/
Dfsl_power.c286 while ((PMC->STATUS & PMC_STATUS_ACTIVEFSM_MASK) != 0U) in POWER_ApplyPD()
291 while ((PMC->STATUS & PMC_STATUS_ACTIVEFSM_MASK) != 0U) in POWER_ApplyPD()
957 …while ((PMC->STATUS & PMC_STATUS_ACTIVEFSM_MASK) != 0U) /* Cannot set APPLYCFG when ACTIVEFSM is 1… in AT_QUICKACCESS_SECTION_CODE()
961 …while ((PMC->STATUS & PMC_STATUS_ACTIVEFSM_MASK) != 0U) /* Wait all PMC finite state machines fini… in AT_QUICKACCESS_SECTION_CODE()
1142 …while ((PMC->STATUS & PMC_STATUS_ACTIVEFSM_MASK) != 0U) /* Cannot set APPLYCFG when ACTIVEFSM is 1… in AT_QUICKACCESS_SECTION_CODE()
1146 …while ((PMC->STATUS & PMC_STATUS_ACTIVEFSM_MASK) != 0U) /* Wait all PMC finite state machines fini… in AT_QUICKACCESS_SECTION_CODE()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/drivers/
Dfsl_power.c286 while ((PMC->STATUS & PMC_STATUS_ACTIVEFSM_MASK) != 0U) in POWER_ApplyPD()
291 while ((PMC->STATUS & PMC_STATUS_ACTIVEFSM_MASK) != 0U) in POWER_ApplyPD()
957 …while ((PMC->STATUS & PMC_STATUS_ACTIVEFSM_MASK) != 0U) /* Cannot set APPLYCFG when ACTIVEFSM is 1… in AT_QUICKACCESS_SECTION_CODE()
961 …while ((PMC->STATUS & PMC_STATUS_ACTIVEFSM_MASK) != 0U) /* Wait all PMC finite state machines fini… in AT_QUICKACCESS_SECTION_CODE()
1142 …while ((PMC->STATUS & PMC_STATUS_ACTIVEFSM_MASK) != 0U) /* Cannot set APPLYCFG when ACTIVEFSM is 1… in AT_QUICKACCESS_SECTION_CODE()
1146 …while ((PMC->STATUS & PMC_STATUS_ACTIVEFSM_MASK) != 0U) /* Wait all PMC finite state machines fini… in AT_QUICKACCESS_SECTION_CODE()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/drivers/
Dfsl_power.c286 while ((PMC->STATUS & PMC_STATUS_ACTIVEFSM_MASK) != 0U) in POWER_ApplyPD()
291 while ((PMC->STATUS & PMC_STATUS_ACTIVEFSM_MASK) != 0U) in POWER_ApplyPD()
957 …while ((PMC->STATUS & PMC_STATUS_ACTIVEFSM_MASK) != 0U) /* Cannot set APPLYCFG when ACTIVEFSM is 1… in AT_QUICKACCESS_SECTION_CODE()
961 …while ((PMC->STATUS & PMC_STATUS_ACTIVEFSM_MASK) != 0U) /* Wait all PMC finite state machines fini… in AT_QUICKACCESS_SECTION_CODE()
1142 …while ((PMC->STATUS & PMC_STATUS_ACTIVEFSM_MASK) != 0U) /* Cannot set APPLYCFG when ACTIVEFSM is 1… in AT_QUICKACCESS_SECTION_CODE()
1146 …while ((PMC->STATUS & PMC_STATUS_ACTIVEFSM_MASK) != 0U) /* Wait all PMC finite state machines fini… in AT_QUICKACCESS_SECTION_CODE()
/hal_nxp-latest/mcux/mcux-sdk/drivers/capt/
Dfsl_capt.h332 base->STATUS = mask; in CAPT_ClearInterruptStatusFlags()
344 return base->STATUS; in CAPT_GetStatusFlags()
/hal_nxp-latest/mcux/mcux-sdk/tools/cmake_toolchain_files/
Darmgcc_aarch64.cmake19 MESSAGE(STATUS "TOOLCHAIN_DIR: " ${TOOLCHAIN_DIR})
56 MESSAGE(STATUS "BUILD_TYPE: " ${CMAKE_BUILD_TYPE})
Dxcc.cmake21 MESSAGE(STATUS "TOOLCHAIN_DIR: " ${TOOLCHAIN_DIR})
65 MESSAGE(STATUS "BUILD_TYPE: " ${CMAKE_BUILD_TYPE})
Dxclang.cmake19 MESSAGE(STATUS "TOOLCHAIN_DIR: " ${TOOLCHAIN_DIR})
62 MESSAGE(STATUS "BUILD_TYPE: " ${CMAKE_BUILD_TYPE})
Darmgcc_force_cpp.cmake19 MESSAGE(STATUS "TOOLCHAIN_DIR: " ${TOOLCHAIN_DIR})
56 MESSAGE(STATUS "BUILD_TYPE: " ${CMAKE_BUILD_TYPE})
Darmgcc.cmake19 MESSAGE(STATUS "TOOLCHAIN_DIR: " ${TOOLCHAIN_DIR})
68 MESSAGE(STATUS "BUILD_TYPE: " ${CMAKE_BUILD_TYPE})
/hal_nxp-latest/mcux/mcux-sdk/drivers/bee/
Dfsl_bee.c289 return base->STATUS; in BEE_GetStatusFlags()
302 base->STATUS |= mask; in BEE_ClearStatusFlags()
/hal_nxp-latest/mcux/mcux-sdk/drivers/ccm32k/
Dfsl_ccm32k.h482 ((base->STATUS & CCM32K_STATUS_OSC32K_RDY_MASK) == 1UL)) \ in CCM32K_SelectClockSource()
517 return base->STATUS; in CCM32K_GetStatusFlag()
/hal_nxp-latest/mcux/mcux-sdk/drivers/dpu/
Dfsl_dpu.c62 __I uint32_t STATUS; member
91 __IO uint32_t STATUS; member
135 __IO uint32_t STATUS; member
163 __IO uint32_t STATUS; member
184 __IO uint32_t STATUS; member
211 __IO uint32_t STATUS; member
372 __IO uint32_t STATUS; member
397 __IO uint32_t STATUS; member
431 __IO uint32_t STATUS; member
3651 return display->SIG.STATUS; in DPU_GetSignatureStatus()

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