Searched refs:SRAM_INT_CLR_ENABLE (Results 1 – 11 of 11) sorted by relevance
| /hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S36/ |
| D | LPC55S36.h | 35813 __O uint32_t SRAM_INT_CLR_ENABLE; /**< Interrupt Enable Clear, offset: 0x3D8 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/ |
| D | MCXN236.h | 45598 __O uint32_t SRAM_INT_CLR_ENABLE; /**< Interrupt Enable Clear, offset: 0x3D8 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/ |
| D | MCXN235.h | 45568 __O uint32_t SRAM_INT_CLR_ENABLE; /**< Interrupt Enable Clear, offset: 0x3D8 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/ |
| D | MCXN546_cm33_core0.h | 57197 __O uint32_t SRAM_INT_CLR_ENABLE; /**< Interrupt Enable Clear, offset: 0x3D8 */ member
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| D | MCXN546_cm33_core1.h | 57197 __O uint32_t SRAM_INT_CLR_ENABLE; /**< Interrupt Enable Clear, offset: 0x3D8 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/ |
| D | MCXN547_cm33_core0.h | 57197 __O uint32_t SRAM_INT_CLR_ENABLE; /**< Interrupt Enable Clear, offset: 0x3D8 */ member
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| D | MCXN547_cm33_core1.h | 57197 __O uint32_t SRAM_INT_CLR_ENABLE; /**< Interrupt Enable Clear, offset: 0x3D8 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/ |
| D | MCXN947_cm33_core1.h | 57932 __O uint32_t SRAM_INT_CLR_ENABLE; /**< Interrupt Enable Clear, offset: 0x3D8 */ member
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| D | MCXN947_cm33_core0.h | 57932 __O uint32_t SRAM_INT_CLR_ENABLE; /**< Interrupt Enable Clear, offset: 0x3D8 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/ |
| D | MCXN946_cm33_core0.h | 57932 __O uint32_t SRAM_INT_CLR_ENABLE; /**< Interrupt Enable Clear, offset: 0x3D8 */ member
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| D | MCXN946_cm33_core1.h | 57932 __O uint32_t SRAM_INT_CLR_ENABLE; /**< Interrupt Enable Clear, offset: 0x3D8 */ member
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