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Searched refs:SPI_FIFOWR_TXSSEL2_N_MASK (Results 1 – 25 of 52) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/LPC51U68/
DLPC51U68.h7501 #define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) macro
7507 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54114/
DLPC54114_cm0plus.h7802 #define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) macro
7808 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
DLPC54114_cm4.h7813 #define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) macro
7819 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54113/
DLPC54113.h7814 #define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) macro
7820 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54607/
DLPC54607.h11965 #define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) macro
11971 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54S005/
DLPC54S005.h11975 #define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) macro
11981 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54005/
DLPC54005.h11183 #define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) macro
11189 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54605/
DLPC54605.h11321 #define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) macro
11327 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54606/
DLPC54606.h15469 #define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) macro
15475 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54016/
DLPC54016.h14543 #define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) macro
14549 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54616/
DLPC54616.h15544 #define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) macro
15550 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54018M/
DLPC54018M.h16076 #define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) macro
16082 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54628/
DLPC54628.h16390 #define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) macro
16396 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5502/
DLPC5502.h20187 #define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) macro
20193 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5502CPXXXX/
DLPC5502CPXXXX.h20070 #define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) macro
20076 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54618/
DLPC54618.h16189 #define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) macro
16195 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54S018/
DLPC54S018.h16868 #define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) macro
16874 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54018/
DLPC54018.h16076 #define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) macro
16082 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54S016/
DLPC54S016.h15249 #define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) macro
15255 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5504CPXXXX/
DLPC5504CPXXXX.h20070 #define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) macro
20076 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5504/
DLPC5504.h20187 #define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) macro
20193 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5506/
DLPC5506.h20187 #define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) macro
20193 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5506CPXXXX/
DLPC5506CPXXXX.h20070 #define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) macro
20076 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54608/
DLPC54608.h16112 #define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) macro
16118 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54S018M/
DLPC54S018M.h16868 #define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) macro
16874 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)

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