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Searched refs:SPI_FIFOCFG_ENABLETX_MASK (Results 1 – 25 of 54) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/components/video/display/dbi/lpc_spi/
Dfsl_dbi_spi_dma.c199 spi->FIFOCFG &= ~SPI_FIFOCFG_ENABLETX_MASK; in DBI_SPI_DMA_WriteMemory()
215 spi->FIFOCFG |= SPI_FIFOCFG_ENABLETX_MASK; in DBI_SPI_DMA_WriteMemory()
/hal_nxp-latest/mcux/mcux-sdk/drivers/flexcomm/spi/
Dfsl_spi.c226 base->FIFOCFG |= SPI_FIFOCFG_ENABLETX_MASK | SPI_FIFOCFG_ENABLERX_MASK; in SPI_MasterInit()
333 base->FIFOCFG |= SPI_FIFOCFG_ENABLETX_MASK | SPI_FIFOCFG_ENABLERX_MASK; in SPI_SlaveInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC51U68/
DLPC51U68.h7221 #define SPI_FIFOCFG_ENABLETX_MASK (0x1U) macro
7227 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54114/
DLPC54114_cm0plus.h7522 #define SPI_FIFOCFG_ENABLETX_MASK (0x1U) macro
7528 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)
DLPC54114_cm4.h7533 #define SPI_FIFOCFG_ENABLETX_MASK (0x1U) macro
7539 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54113/
DLPC54113.h7534 #define SPI_FIFOCFG_ENABLETX_MASK (0x1U) macro
7540 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54607/
DLPC54607.h11639 #define SPI_FIFOCFG_ENABLETX_MASK (0x1U) macro
11645 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54S005/
DLPC54S005.h11657 #define SPI_FIFOCFG_ENABLETX_MASK (0x1U) macro
11663 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54005/
DLPC54005.h10865 #define SPI_FIFOCFG_ENABLETX_MASK (0x1U) macro
10871 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54605/
DLPC54605.h10995 #define SPI_FIFOCFG_ENABLETX_MASK (0x1U) macro
11001 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54606/
DLPC54606.h15143 #define SPI_FIFOCFG_ENABLETX_MASK (0x1U) macro
15149 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54016/
DLPC54016.h14239 #define SPI_FIFOCFG_ENABLETX_MASK (0x1U) macro
14245 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54616/
DLPC54616.h15218 #define SPI_FIFOCFG_ENABLETX_MASK (0x1U) macro
15224 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54018M/
DLPC54018M.h15758 #define SPI_FIFOCFG_ENABLETX_MASK (0x1U) macro
15764 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54628/
DLPC54628.h16064 #define SPI_FIFOCFG_ENABLETX_MASK (0x1U) macro
16070 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5502/
DLPC5502.h19869 #define SPI_FIFOCFG_ENABLETX_MASK (0x1U) macro
19875 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5502CPXXXX/
DLPC5502CPXXXX.h19752 #define SPI_FIFOCFG_ENABLETX_MASK (0x1U) macro
19758 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54618/
DLPC54618.h15863 #define SPI_FIFOCFG_ENABLETX_MASK (0x1U) macro
15869 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54S018/
DLPC54S018.h16550 #define SPI_FIFOCFG_ENABLETX_MASK (0x1U) macro
16556 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54018/
DLPC54018.h15758 #define SPI_FIFOCFG_ENABLETX_MASK (0x1U) macro
15764 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54S016/
DLPC54S016.h14945 #define SPI_FIFOCFG_ENABLETX_MASK (0x1U) macro
14951 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5504CPXXXX/
DLPC5504CPXXXX.h19752 #define SPI_FIFOCFG_ENABLETX_MASK (0x1U) macro
19758 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5504/
DLPC5504.h19869 #define SPI_FIFOCFG_ENABLETX_MASK (0x1U) macro
19875 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5506/
DLPC5506.h19869 #define SPI_FIFOCFG_ENABLETX_MASK (0x1U) macro
19875 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5506CPXXXX/
DLPC5506CPXXXX.h19752 #define SPI_FIFOCFG_ENABLETX_MASK (0x1U) macro
19758 … (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)

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