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Searched refs:SINC_CCR_CADEN_MASK (Results 1 – 10 of 10) sorted by relevance

/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_SINC.h793 #define SINC_CCR_CADEN_MASK (0x200U) macro
796 … (((uint32_t)(((uint32_t)(x)) << SINC_CCR_CADEN_SHIFT)) & SINC_CCR_CADEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/drivers/sinc/
Dfsl_sinc.h1770 base->CHANNEL[(uint8_t)chId].CCR &= ~SINC_CCR_CADEN_MASK; in SINC_SetChannelCadLimitThreshold()
1774 base->CHANNEL[(uint8_t)chId].CCR |= SINC_CCR_CADEN_MASK; in SINC_SetChannelCadLimitThreshold()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h70515 #define SINC_CCR_CADEN_MASK (0x200U) macro
70521 … (((uint32_t)(((uint32_t)(x)) << SINC_CCR_CADEN_SHIFT)) & SINC_CCR_CADEN_MASK)
DMCXN947_cm33_core0.h70515 #define SINC_CCR_CADEN_MASK (0x200U) macro
70521 … (((uint32_t)(((uint32_t)(x)) << SINC_CCR_CADEN_SHIFT)) & SINC_CCR_CADEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h70515 #define SINC_CCR_CADEN_MASK (0x200U) macro
70521 … (((uint32_t)(((uint32_t)(x)) << SINC_CCR_CADEN_SHIFT)) & SINC_CCR_CADEN_MASK)
DMCXN946_cm33_core1.h70515 #define SINC_CCR_CADEN_MASK (0x200U) macro
70521 … (((uint32_t)(((uint32_t)(x)) << SINC_CCR_CADEN_SHIFT)) & SINC_CCR_CADEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1187/
DMIMXRT1187_cm33.h77103 #define SINC_CCR_CADEN_MASK (0x200U) macro
77109 … (((uint32_t)(((uint32_t)(x)) << SINC_CCR_CADEN_SHIFT)) & SINC_CCR_CADEN_MASK)
DMIMXRT1187_cm7.h75058 #define SINC_CCR_CADEN_MASK (0x200U) macro
75064 … (((uint32_t)(((uint32_t)(x)) << SINC_CCR_CADEN_SHIFT)) & SINC_CCR_CADEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1189/
DMIMXRT1189_cm33.h80951 #define SINC_CCR_CADEN_MASK (0x200U) macro
80957 … (((uint32_t)(((uint32_t)(x)) << SINC_CCR_CADEN_SHIFT)) & SINC_CCR_CADEN_MASK)
DMIMXRT1189_cm7.h78887 #define SINC_CCR_CADEN_MASK (0x200U) macro
78893 … (((uint32_t)(((uint32_t)(x)) << SINC_CCR_CADEN_SHIFT)) & SINC_CCR_CADEN_MASK)