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Searched refs:SIM_UIDH_UID127_96_MASK (Results 1 – 25 of 27) sorted by relevance

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/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K116_SIM.h377 #define SIM_UIDH_UID127_96_MASK (0xFFFFFFFFU) macro
380 … (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID127_96_SHIFT)) & SIM_UIDH_UID127_96_MASK)
DS32K118_SIM.h377 #define SIM_UIDH_UID127_96_MASK (0xFFFFFFFFU) macro
380 … (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID127_96_SHIFT)) & SIM_UIDH_UID127_96_MASK)
DS32K142W_SIM.h468 #define SIM_UIDH_UID127_96_MASK (0xFFFFFFFFU) macro
471 … (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID127_96_SHIFT)) & SIM_UIDH_UID127_96_MASK)
DS32K142_SIM.h448 #define SIM_UIDH_UID127_96_MASK (0xFFFFFFFFU) macro
451 … (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID127_96_SHIFT)) & SIM_UIDH_UID127_96_MASK)
DS32K144W_SIM.h468 #define SIM_UIDH_UID127_96_MASK (0xFFFFFFFFU) macro
471 … (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID127_96_SHIFT)) & SIM_UIDH_UID127_96_MASK)
DS32K144_SIM.h448 #define SIM_UIDH_UID127_96_MASK (0xFFFFFFFFU) macro
451 … (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID127_96_SHIFT)) & SIM_UIDH_UID127_96_MASK)
DS32K146_SIM.h493 #define SIM_UIDH_UID127_96_MASK (0xFFFFFFFFU) macro
496 … (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID127_96_SHIFT)) & SIM_UIDH_UID127_96_MASK)
DS32K148_SIM.h528 #define SIM_UIDH_UID127_96_MASK (0xFFFFFFFFU) macro
531 … (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID127_96_SHIFT)) & SIM_UIDH_UID127_96_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z4/
DMKE14Z4.h10623 #define SIM_UIDH_UID127_96_MASK (0xFFFFFFFFU) macro
10627 … (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID127_96_SHIFT)) & SIM_UIDH_UID127_96_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z4/
DMKE15Z4.h10625 #define SIM_UIDH_UID127_96_MASK (0xFFFFFFFFU) macro
10629 … (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID127_96_SHIFT)) & SIM_UIDH_UID127_96_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKM14ZA5/
DMKM14ZA5.h10312 #define SIM_UIDH_UID127_96_MASK (0xFFFFFFFFU) macro
10316 … (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID127_96_SHIFT)) & SIM_UIDH_UID127_96_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE16Z4/
DMKE16Z4.h11462 #define SIM_UIDH_UID127_96_MASK (0xFFFFFFFFU) macro
11466 … (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID127_96_SHIFT)) & SIM_UIDH_UID127_96_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z7/
DMKE12Z7.h13263 #define SIM_UIDH_UID127_96_MASK (0xFFFFFFFFU) macro
13267 … (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID127_96_SHIFT)) & SIM_UIDH_UID127_96_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z9/
DMKE12Z9.h13238 #define SIM_UIDH_UID127_96_MASK (0xFFFFFFFFU) macro
13241 … (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID127_96_SHIFT)) & SIM_UIDH_UID127_96_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z7/
DMKE17Z7.h13269 #define SIM_UIDH_UID127_96_MASK (0xFFFFFFFFU) macro
13273 … (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID127_96_SHIFT)) & SIM_UIDH_UID127_96_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z7/
DMKE13Z7.h13266 #define SIM_UIDH_UID127_96_MASK (0xFFFFFFFFU) macro
13270 … (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID127_96_SHIFT)) & SIM_UIDH_UID127_96_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z7/
DMKE14Z7.h13499 #define SIM_UIDH_UID127_96_MASK (0xFFFFFFFFU) macro
13503 … (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID127_96_SHIFT)) & SIM_UIDH_UID127_96_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z9/
DMKE17Z9.h13242 #define SIM_UIDH_UID127_96_MASK (0xFFFFFFFFU) macro
13245 … (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID127_96_SHIFT)) & SIM_UIDH_UID127_96_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z7/
DMKE15Z7.h13502 #define SIM_UIDH_UID127_96_MASK (0xFFFFFFFFU) macro
13506 … (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID127_96_SHIFT)) & SIM_UIDH_UID127_96_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z9/
DMKE13Z9.h13240 #define SIM_UIDH_UID127_96_MASK (0xFFFFFFFFU) macro
13243 … (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID127_96_SHIFT)) & SIM_UIDH_UID127_96_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14F16/
DMKE14F16.h16818 #define SIM_UIDH_UID127_96_MASK (0xFFFFFFFFU) macro
16822 … (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID127_96_SHIFT)) & SIM_UIDH_UID127_96_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKM33ZA5/
DMKM33ZA5.h15017 #define SIM_UIDH_UID127_96_MASK (0xFFFFFFFFU) macro
15021 … (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID127_96_SHIFT)) & SIM_UIDH_UID127_96_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE18F16/
DMKE18F16.h17824 #define SIM_UIDH_UID127_96_MASK (0xFFFFFFFFU) macro
17828 … (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID127_96_SHIFT)) & SIM_UIDH_UID127_96_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE16F16/
DMKE16F16.h17818 #define SIM_UIDH_UID127_96_MASK (0xFFFFFFFFU) macro
17822 … (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID127_96_SHIFT)) & SIM_UIDH_UID127_96_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKM34ZA5/
DMKM34ZA5.h15013 #define SIM_UIDH_UID127_96_MASK (0xFFFFFFFFU) macro
15017 … (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID127_96_SHIFT)) & SIM_UIDH_UID127_96_MASK)

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