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Searched refs:SEC_CPU1_INT_MASK4 (Results 1 – 8 of 8) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h1717 …__IO uint32_t SEC_CPU1_INT_MASK4; /**< Secure Interrupt Mask 4 for CPU1, offset: 0x… member
DMCXN546_cm33_core1.h1717 …__IO uint32_t SEC_CPU1_INT_MASK4; /**< Secure Interrupt Mask 4 for CPU1, offset: 0x… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h1717 …__IO uint32_t SEC_CPU1_INT_MASK4; /**< Secure Interrupt Mask 4 for CPU1, offset: 0x… member
DMCXN547_cm33_core1.h1717 …__IO uint32_t SEC_CPU1_INT_MASK4; /**< Secure Interrupt Mask 4 for CPU1, offset: 0x… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h1751 …__IO uint32_t SEC_CPU1_INT_MASK4; /**< Secure Interrupt Mask 4 for CPU1, offset: 0x… member
DMCXN947_cm33_core0.h1751 …__IO uint32_t SEC_CPU1_INT_MASK4; /**< Secure Interrupt Mask 4 for CPU1, offset: 0x… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h1751 …__IO uint32_t SEC_CPU1_INT_MASK4; /**< Secure Interrupt Mask 4 for CPU1, offset: 0x… member
DMCXN946_cm33_core1.h1751 …__IO uint32_t SEC_CPU1_INT_MASK4; /**< Secure Interrupt Mask 4 for CPU1, offset: 0x… member