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Searched refs:SEC_CLK_CTRL (Results 1 – 16 of 16) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/drivers/
Dfsl_clock.c111 while ((SYSCON0->SEC_CLK_CTRL & bitMask) == 0U) in CLOCK_EnableClock()
185 while ((SYSCON3->SEC_CLK_CTRL & bitMask) == 0U) in CLOCK_EnableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/drivers/
Dfsl_clock.c111 while ((SYSCON0->SEC_CLK_CTRL & bitMask) == 0U) in CLOCK_EnableClock()
185 while ((SYSCON3->SEC_CLK_CTRL & bitMask) == 0U) in CLOCK_EnableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/drivers/
Dfsl_clock.c111 while ((SYSCON0->SEC_CLK_CTRL & bitMask) == 0U) in CLOCK_EnableClock()
185 while ((SYSCON3->SEC_CLK_CTRL & bitMask) == 0U) in CLOCK_EnableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi4.h75038 __IO uint32_t SEC_CLK_CTRL; /**< Security Clock Control, offset: 0x0 */ member
79380 __IO uint32_t SEC_CLK_CTRL; /**< Security Clock Control, offset: 0x0 */ member
DMIMXRT798S_cm33_core0.h75125 __IO uint32_t SEC_CLK_CTRL; /**< Security Clock Control, offset: 0x0 */ member
79467 __IO uint32_t SEC_CLK_CTRL; /**< Security Clock Control, offset: 0x0 */ member
DMIMXRT798S_ezhv.h78767 __IO uint32_t SEC_CLK_CTRL; /**< Security Clock Control, offset: 0x0 */ member
84330 __IO uint32_t SEC_CLK_CTRL; /**< Security Clock Control, offset: 0x0 */ member
DMIMXRT798S_hifi1.h56379 __IO uint32_t SEC_CLK_CTRL; /**< Security Clock Control, offset: 0x0 */ member
DMIMXRT798S_cm33_core1.h56441 __IO uint32_t SEC_CLK_CTRL; /**< Security Clock Control, offset: 0x0 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_ezhv.h75598 __IO uint32_t SEC_CLK_CTRL; /**< Security Clock Control, offset: 0x0 */ member
81161 __IO uint32_t SEC_CLK_CTRL; /**< Security Clock Control, offset: 0x0 */ member
DMIMXRT735S_cm33_core0.h71900 __IO uint32_t SEC_CLK_CTRL; /**< Security Clock Control, offset: 0x0 */ member
76242 __IO uint32_t SEC_CLK_CTRL; /**< Security Clock Control, offset: 0x0 */ member
DMIMXRT735S_hifi1.h53158 __IO uint32_t SEC_CLK_CTRL; /**< Security Clock Control, offset: 0x0 */ member
DMIMXRT735S_cm33_core1.h53218 __IO uint32_t SEC_CLK_CTRL; /**< Security Clock Control, offset: 0x0 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core0.h75125 __IO uint32_t SEC_CLK_CTRL; /**< Security Clock Control, offset: 0x0 */ member
79467 __IO uint32_t SEC_CLK_CTRL; /**< Security Clock Control, offset: 0x0 */ member
DMIMXRT758S_ezhv.h78743 __IO uint32_t SEC_CLK_CTRL; /**< Security Clock Control, offset: 0x0 */ member
84306 __IO uint32_t SEC_CLK_CTRL; /**< Security Clock Control, offset: 0x0 */ member
DMIMXRT758S_cm33_core1.h56441 __IO uint32_t SEC_CLK_CTRL; /**< Security Clock Control, offset: 0x0 */ member
DMIMXRT758S_hifi1.h56379 __IO uint32_t SEC_CLK_CTRL; /**< Security Clock Control, offset: 0x0 */ member