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Searched refs:SCG_SPLLCTRL_SELR_MASK (Results 1 – 10 of 10) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h53561 #define SCG_SPLLCTRL_SELR_MASK (0xFU) macro
53564 … (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_SELR_SHIFT)) & SCG_SPLLCTRL_SELR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h53519 #define SCG_SPLLCTRL_SELR_MASK (0xFU) macro
53522 … (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_SELR_SHIFT)) & SCG_SPLLCTRL_SELR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h65096 #define SCG_SPLLCTRL_SELR_MASK (0xFU) macro
65099 … (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_SELR_SHIFT)) & SCG_SPLLCTRL_SELR_MASK)
DMCXN546_cm33_core1.h65096 #define SCG_SPLLCTRL_SELR_MASK (0xFU) macro
65099 … (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_SELR_SHIFT)) & SCG_SPLLCTRL_SELR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h65096 #define SCG_SPLLCTRL_SELR_MASK (0xFU) macro
65099 … (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_SELR_SHIFT)) & SCG_SPLLCTRL_SELR_MASK)
DMCXN547_cm33_core1.h65096 #define SCG_SPLLCTRL_SELR_MASK (0xFU) macro
65099 … (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_SELR_SHIFT)) & SCG_SPLLCTRL_SELR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h65843 #define SCG_SPLLCTRL_SELR_MASK (0xFU) macro
65846 … (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_SELR_SHIFT)) & SCG_SPLLCTRL_SELR_MASK)
DMCXN947_cm33_core0.h65843 #define SCG_SPLLCTRL_SELR_MASK (0xFU) macro
65846 … (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_SELR_SHIFT)) & SCG_SPLLCTRL_SELR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h65843 #define SCG_SPLLCTRL_SELR_MASK (0xFU) macro
65846 … (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_SELR_SHIFT)) & SCG_SPLLCTRL_SELR_MASK)
DMCXN946_cm33_core1.h65843 #define SCG_SPLLCTRL_SELR_MASK (0xFU) macro
65846 … (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_SELR_SHIFT)) & SCG_SPLLCTRL_SELR_MASK)