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Searched refs:SCG_APLLMDIV_MREQ_MASK (Results 1 – 10 of 10) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h53323 #define SCG_APLLMDIV_MREQ_MASK (0x80000000U) macro
53329 … (((uint32_t)(((uint32_t)(x)) << SCG_APLLMDIV_MREQ_SHIFT)) & SCG_APLLMDIV_MREQ_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h53281 #define SCG_APLLMDIV_MREQ_MASK (0x80000000U) macro
53287 … (((uint32_t)(((uint32_t)(x)) << SCG_APLLMDIV_MREQ_SHIFT)) & SCG_APLLMDIV_MREQ_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h64866 #define SCG_APLLMDIV_MREQ_MASK (0x80000000U) macro
64872 … (((uint32_t)(((uint32_t)(x)) << SCG_APLLMDIV_MREQ_SHIFT)) & SCG_APLLMDIV_MREQ_MASK)
DMCXN546_cm33_core1.h64866 #define SCG_APLLMDIV_MREQ_MASK (0x80000000U) macro
64872 … (((uint32_t)(((uint32_t)(x)) << SCG_APLLMDIV_MREQ_SHIFT)) & SCG_APLLMDIV_MREQ_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h64866 #define SCG_APLLMDIV_MREQ_MASK (0x80000000U) macro
64872 … (((uint32_t)(((uint32_t)(x)) << SCG_APLLMDIV_MREQ_SHIFT)) & SCG_APLLMDIV_MREQ_MASK)
DMCXN547_cm33_core1.h64866 #define SCG_APLLMDIV_MREQ_MASK (0x80000000U) macro
64872 … (((uint32_t)(((uint32_t)(x)) << SCG_APLLMDIV_MREQ_SHIFT)) & SCG_APLLMDIV_MREQ_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h65613 #define SCG_APLLMDIV_MREQ_MASK (0x80000000U) macro
65619 … (((uint32_t)(((uint32_t)(x)) << SCG_APLLMDIV_MREQ_SHIFT)) & SCG_APLLMDIV_MREQ_MASK)
DMCXN947_cm33_core0.h65613 #define SCG_APLLMDIV_MREQ_MASK (0x80000000U) macro
65619 … (((uint32_t)(((uint32_t)(x)) << SCG_APLLMDIV_MREQ_SHIFT)) & SCG_APLLMDIV_MREQ_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h65613 #define SCG_APLLMDIV_MREQ_MASK (0x80000000U) macro
65619 … (((uint32_t)(((uint32_t)(x)) << SCG_APLLMDIV_MREQ_SHIFT)) & SCG_APLLMDIV_MREQ_MASK)
DMCXN946_cm33_core1.h65613 #define SCG_APLLMDIV_MREQ_MASK (0x80000000U) macro
65619 … (((uint32_t)(((uint32_t)(x)) << SCG_APLLMDIV_MREQ_SHIFT)) & SCG_APLLMDIV_MREQ_MASK)