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Searched refs:SCG_APLLCSR_APLLCLKEN_MASK (Results 1 – 16 of 16) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/drivers/
Dfsl_clock.c1725 SCG0->APLLCSR &= ~(SCG_APLLCSR_APLLPWREN_MASK | SCG_APLLCSR_APLLCLKEN_MASK); in CLOCK_SetPLL0Freq()
1749 SCG0->APLLCSR |= (SCG_APLLCSR_APLLPWREN_MASK | SCG_APLLCSR_APLLCLKEN_MASK); in CLOCK_SetPLL0Freq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/drivers/
Dfsl_clock.c1725 SCG0->APLLCSR &= ~(SCG_APLLCSR_APLLPWREN_MASK | SCG_APLLCSR_APLLCLKEN_MASK); in CLOCK_SetPLL0Freq()
1749 SCG0->APLLCSR |= (SCG_APLLCSR_APLLPWREN_MASK | SCG_APLLCSR_APLLCLKEN_MASK); in CLOCK_SetPLL0Freq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/drivers/
Dfsl_clock.c2139 SCG0->APLLCSR &= ~(SCG_APLLCSR_APLLPWREN_MASK | SCG_APLLCSR_APLLCLKEN_MASK); in CLOCK_SetPLL0Freq()
2163 SCG0->APLLCSR |= (SCG_APLLCSR_APLLPWREN_MASK | SCG_APLLCSR_APLLCLKEN_MASK); in CLOCK_SetPLL0Freq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/drivers/
Dfsl_clock.c2139 SCG0->APLLCSR &= ~(SCG_APLLCSR_APLLPWREN_MASK | SCG_APLLCSR_APLLCLKEN_MASK); in CLOCK_SetPLL0Freq()
2163 SCG0->APLLCSR |= (SCG_APLLCSR_APLLPWREN_MASK | SCG_APLLCSR_APLLCLKEN_MASK); in CLOCK_SetPLL0Freq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/drivers/
Dfsl_clock.c2139 SCG0->APLLCSR &= ~(SCG_APLLCSR_APLLPWREN_MASK | SCG_APLLCSR_APLLCLKEN_MASK); in CLOCK_SetPLL0Freq()
2163 SCG0->APLLCSR |= (SCG_APLLCSR_APLLPWREN_MASK | SCG_APLLCSR_APLLCLKEN_MASK); in CLOCK_SetPLL0Freq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/drivers/
Dfsl_clock.c2139 SCG0->APLLCSR &= ~(SCG_APLLCSR_APLLPWREN_MASK | SCG_APLLCSR_APLLCLKEN_MASK); in CLOCK_SetPLL0Freq()
2163 SCG0->APLLCSR |= (SCG_APLLCSR_APLLPWREN_MASK | SCG_APLLCSR_APLLCLKEN_MASK); in CLOCK_SetPLL0Freq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h53104 #define SCG_APLLCSR_APLLCLKEN_MASK (0x2U) macro
53110 … (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLCLKEN_SHIFT)) & SCG_APLLCSR_APLLCLKEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h53062 #define SCG_APLLCSR_APLLCLKEN_MASK (0x2U) macro
53068 … (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLCLKEN_SHIFT)) & SCG_APLLCSR_APLLCLKEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h64671 #define SCG_APLLCSR_APLLCLKEN_MASK (0x2U) macro
64677 … (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLCLKEN_SHIFT)) & SCG_APLLCSR_APLLCLKEN_MASK)
DMCXN546_cm33_core1.h64671 #define SCG_APLLCSR_APLLCLKEN_MASK (0x2U) macro
64677 … (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLCLKEN_SHIFT)) & SCG_APLLCSR_APLLCLKEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h64671 #define SCG_APLLCSR_APLLCLKEN_MASK (0x2U) macro
64677 … (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLCLKEN_SHIFT)) & SCG_APLLCSR_APLLCLKEN_MASK)
DMCXN547_cm33_core1.h64671 #define SCG_APLLCSR_APLLCLKEN_MASK (0x2U) macro
64677 … (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLCLKEN_SHIFT)) & SCG_APLLCSR_APLLCLKEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h65418 #define SCG_APLLCSR_APLLCLKEN_MASK (0x2U) macro
65424 … (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLCLKEN_SHIFT)) & SCG_APLLCSR_APLLCLKEN_MASK)
DMCXN947_cm33_core0.h65418 #define SCG_APLLCSR_APLLCLKEN_MASK (0x2U) macro
65424 … (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLCLKEN_SHIFT)) & SCG_APLLCSR_APLLCLKEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h65418 #define SCG_APLLCSR_APLLCLKEN_MASK (0x2U) macro
65424 … (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLCLKEN_SHIFT)) & SCG_APLLCSR_APLLCLKEN_MASK)
DMCXN946_cm33_core1.h65418 #define SCG_APLLCSR_APLLCLKEN_MASK (0x2U) macro
65424 … (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLCLKEN_SHIFT)) & SCG_APLLCSR_APLLCLKEN_MASK)