Home
last modified time | relevance | path

Searched refs:SARADCFCLKDIV_OFFSET (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/drivers/
Dfsl_clock.h915 #define SARADCFCLKDIV_OFFSET 0x624 macro
1739 …kCLOCK_DivAdcClk = CLKCTL3_TUPLE_MUXA(SARADCFCLKDIV_OFFSET, 0), /*!< SARADC Clk Divide…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/drivers/
Dfsl_clock.h915 #define SARADCFCLKDIV_OFFSET 0x624 macro
1739 …kCLOCK_DivAdcClk = CLKCTL3_TUPLE_MUXA(SARADCFCLKDIV_OFFSET, 0), /*!< SARADC Clk Divide…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/drivers/
Dfsl_clock.h915 #define SARADCFCLKDIV_OFFSET 0x624 macro
1739 …kCLOCK_DivAdcClk = CLKCTL3_TUPLE_MUXA(SARADCFCLKDIV_OFFSET, 0), /*!< SARADC Clk Divide…