1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_NVIC.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_NVIC 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_NVIC_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_NVIC_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- S32_NVIC Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup S32_NVIC_Peripheral_Access_Layer S32_NVIC Peripheral Access Layer 68 * @{ 69 */ 70 71 /** S32_NVIC - Size of Registers Arrays */ 72 #define S32_NVIC_ISER_COUNT 16u 73 #define S32_NVIC_ICER_COUNT 16u 74 #define S32_NVIC_ISPR_COUNT 16u 75 #define S32_NVIC_ICPR_COUNT 16u 76 #define S32_NVIC_IABR_COUNT 16u 77 #define S32_NVIC_ITNS_COUNT 16u 78 #define S32_NVIC_IP_COUNT 480u 79 80 /** S32_NVIC - Register Layout Typedef */ 81 typedef struct { 82 uint8_t RESERVED_0[4]; 83 __I uint32_t ICTR; /**< Interrupt Control Type Register, offset: 0x4 */ 84 uint8_t RESERVED_1[248]; 85 __IO uint32_t ISER[S32_NVIC_ISER_COUNT]; /**< Interrupt Set Enable Register n, array offset: 0x100, array step: 0x4 */ 86 uint8_t RESERVED_2[64]; 87 __IO uint32_t ICER[S32_NVIC_ICER_COUNT]; /**< Interrupt Clear Enable Register n, array offset: 0x180, array step: 0x4 */ 88 uint8_t RESERVED_3[64]; 89 __IO uint32_t ISPR[S32_NVIC_ISPR_COUNT]; /**< Interrupt Set Pending Register n, array offset: 0x200, array step: 0x4 */ 90 uint8_t RESERVED_4[64]; 91 __IO uint32_t ICPR[S32_NVIC_ICPR_COUNT]; /**< Interrupt Clear Pending Register n, array offset: 0x280, array step: 0x4 */ 92 uint8_t RESERVED_5[64]; 93 __IO uint32_t IABR[S32_NVIC_IABR_COUNT]; /**< Interrupt Active bit Register n, array offset: 0x300, array step: 0x4 */ 94 uint8_t RESERVED_6[64]; 95 __IO uint32_t ITNS[S32_NVIC_ITNS_COUNT]; /**< Interrupt Target Non-Secure Register n, array offset: 0x380, array step: 0x4 (Not accessible from S32_NVIC_NS) */ 96 uint8_t RESERVED_7[64]; 97 __IO uint8_t IP[S32_NVIC_IP_COUNT]; /**< Interrupt Priority Register n, array offset: 0x400, array step: 0x1 */ 98 uint8_t RESERVED_8[2576]; 99 __O uint32_t STIR; /**< Software Trigger Interrupt Register, offset: 0xF00 */ 100 } S32_NVIC_Type, *S32_NVIC_MemMapPtr; 101 102 /** Number of instances of the S32_NVIC module. */ 103 #define S32_NVIC_INSTANCE_COUNT (1u) 104 105 /* S32_NVIC - Peripheral instance base addresses */ 106 /** Peripheral S32_NVIC base address */ 107 #define IP_S32_NVIC_BASE (0xE000E000u) 108 /** Peripheral S32_NVIC_NS base address */ 109 #define IP_S32_NVIC_NS_BASE (0xE002E000u) 110 /** Peripheral S32_NVIC base pointer */ 111 #define S32_NVIC ((S32_NVIC_Type *)IP_S32_NVIC_BASE) 112 /** Peripheral S32_NVIC_NS base pointer */ 113 #define S32_NVIC_NS ((S32_NVIC_Type *)IP_S32_NVIC_NS_BASE) 114 /** Array initializer of S32_NVIC peripheral base addresses */ 115 #define IP_S32_NVIC_BASE_ADDRS { IP_S32_NVIC_BASE } 116 /** Array initializer of S32_NVIC peripheral base pointers */ 117 #define IP_S32_NVIC_BASE_PTRS { IP_S32_NVIC } 118 119 /* ---------------------------------------------------------------------------- 120 -- S32_NVIC Register Masks 121 ---------------------------------------------------------------------------- */ 122 123 /*! 124 * @addtogroup S32_NVIC_Register_Masks S32_NVIC Register Masks 125 * @{ 126 */ 127 128 /* ICTR Bit Fields */ 129 #define S32_NVIC_ICTR_ICTR_MASK 0xFFFFFFFFu 130 #define S32_NVIC_ICTR_ICTR_SHIFT 0u 131 #define S32_NVIC_ICTR_ICTR_WIDTH 32u 132 #define S32_NVIC_ICTR_ICTR(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_ICTR_ICTR_SHIFT))&S32_NVIC_ICTR_ICTR_MASK) 133 /* ISER Bit Fields */ 134 #define S32_NVIC_ISER_SETENA_MASK 0xFFFFFFFFu 135 #define S32_NVIC_ISER_SETENA_SHIFT 0u 136 #define S32_NVIC_ISER_SETENA_WIDTH 32u 137 #define S32_NVIC_ISER_SETENA(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_ISER_SETENA_SHIFT))&S32_NVIC_ISER_SETENA_MASK) 138 /* ICER Bit Fields */ 139 #define S32_NVIC_ICER_CLRENA_MASK 0xFFFFFFFFu 140 #define S32_NVIC_ICER_CLRENA_SHIFT 0u 141 #define S32_NVIC_ICER_CLRENA_WIDTH 32u 142 #define S32_NVIC_ICER_CLRENA(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_ICER_CLRENA_SHIFT))&S32_NVIC_ICER_CLRENA_MASK) 143 /* ISPR Bit Fields */ 144 #define S32_NVIC_ISPR_SETPEND_MASK 0xFFFFFFFFu 145 #define S32_NVIC_ISPR_SETPEND_SHIFT 0u 146 #define S32_NVIC_ISPR_SETPEND_WIDTH 32u 147 #define S32_NVIC_ISPR_SETPEND(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_ISPR_SETPEND_SHIFT))&S32_NVIC_ISPR_SETPEND_MASK) 148 /* ICPR Bit Fields */ 149 #define S32_NVIC_ICPR_CLRPEND_MASK 0xFFFFFFFFu 150 #define S32_NVIC_ICPR_CLRPEND_SHIFT 0u 151 #define S32_NVIC_ICPR_CLRPEND_WIDTH 32u 152 #define S32_NVIC_ICPR_CLRPEND(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_ICPR_CLRPEND_SHIFT))&S32_NVIC_ICPR_CLRPEND_MASK) 153 /* IABR Bit Fields */ 154 #define S32_NVIC_IABR_ACTIVE_MASK 0xFFFFFFFFu 155 #define S32_NVIC_IABR_ACTIVE_SHIFT 0u 156 #define S32_NVIC_IABR_ACTIVE_WIDTH 32u 157 #define S32_NVIC_IABR_ACTIVE(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_IABR_ACTIVE_SHIFT))&S32_NVIC_IABR_ACTIVE_MASK) 158 /* IP Bit Fields */ 159 #define S32_NVIC_IP_PRI0_MASK 0xFFu 160 #define S32_NVIC_IP_PRI0_SHIFT 0u 161 #define S32_NVIC_IP_PRI0_WIDTH 8u 162 #define S32_NVIC_IP_PRI0(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI0_SHIFT))&S32_NVIC_IP_PRI0_MASK) 163 #define S32_NVIC_IP_PRI1_MASK 0xFFu 164 #define S32_NVIC_IP_PRI1_SHIFT 0u 165 #define S32_NVIC_IP_PRI1_WIDTH 8u 166 #define S32_NVIC_IP_PRI1(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI1_SHIFT))&S32_NVIC_IP_PRI1_MASK) 167 #define S32_NVIC_IP_PRI2_MASK 0xFFu 168 #define S32_NVIC_IP_PRI2_SHIFT 0u 169 #define S32_NVIC_IP_PRI2_WIDTH 8u 170 #define S32_NVIC_IP_PRI2(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI2_SHIFT))&S32_NVIC_IP_PRI2_MASK) 171 #define S32_NVIC_IP_PRI3_MASK 0xFFu 172 #define S32_NVIC_IP_PRI3_SHIFT 0u 173 #define S32_NVIC_IP_PRI3_WIDTH 8u 174 #define S32_NVIC_IP_PRI3(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI3_SHIFT))&S32_NVIC_IP_PRI3_MASK) 175 #define S32_NVIC_IP_PRI4_MASK 0xFFu 176 #define S32_NVIC_IP_PRI4_SHIFT 0u 177 #define S32_NVIC_IP_PRI4_WIDTH 8u 178 #define S32_NVIC_IP_PRI4(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI4_SHIFT))&S32_NVIC_IP_PRI4_MASK) 179 #define S32_NVIC_IP_PRI5_MASK 0xFFu 180 #define S32_NVIC_IP_PRI5_SHIFT 0u 181 #define S32_NVIC_IP_PRI5_WIDTH 8u 182 #define S32_NVIC_IP_PRI5(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI5_SHIFT))&S32_NVIC_IP_PRI5_MASK) 183 #define S32_NVIC_IP_PRI6_MASK 0xFFu 184 #define S32_NVIC_IP_PRI6_SHIFT 0u 185 #define S32_NVIC_IP_PRI6_WIDTH 8u 186 #define S32_NVIC_IP_PRI6(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI6_SHIFT))&S32_NVIC_IP_PRI6_MASK) 187 #define S32_NVIC_IP_PRI7_MASK 0xFFu 188 #define S32_NVIC_IP_PRI7_SHIFT 0u 189 #define S32_NVIC_IP_PRI7_WIDTH 8u 190 #define S32_NVIC_IP_PRI7(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI7_SHIFT))&S32_NVIC_IP_PRI7_MASK) 191 #define S32_NVIC_IP_PRI8_MASK 0xFFu 192 #define S32_NVIC_IP_PRI8_SHIFT 0u 193 #define S32_NVIC_IP_PRI8_WIDTH 8u 194 #define S32_NVIC_IP_PRI8(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI8_SHIFT))&S32_NVIC_IP_PRI8_MASK) 195 #define S32_NVIC_IP_PRI9_MASK 0xFFu 196 #define S32_NVIC_IP_PRI9_SHIFT 0u 197 #define S32_NVIC_IP_PRI9_WIDTH 8u 198 #define S32_NVIC_IP_PRI9(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI9_SHIFT))&S32_NVIC_IP_PRI9_MASK) 199 #define S32_NVIC_IP_PRI10_MASK 0xFFu 200 #define S32_NVIC_IP_PRI10_SHIFT 0u 201 #define S32_NVIC_IP_PRI10_WIDTH 8u 202 #define S32_NVIC_IP_PRI10(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI10_SHIFT))&S32_NVIC_IP_PRI10_MASK) 203 #define S32_NVIC_IP_PRI11_MASK 0xFFu 204 #define S32_NVIC_IP_PRI11_SHIFT 0u 205 #define S32_NVIC_IP_PRI11_WIDTH 8u 206 #define S32_NVIC_IP_PRI11(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI11_SHIFT))&S32_NVIC_IP_PRI11_MASK) 207 #define S32_NVIC_IP_PRI12_MASK 0xFFu 208 #define S32_NVIC_IP_PRI12_SHIFT 0u 209 #define S32_NVIC_IP_PRI12_WIDTH 8u 210 #define S32_NVIC_IP_PRI12(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI12_SHIFT))&S32_NVIC_IP_PRI12_MASK) 211 #define S32_NVIC_IP_PRI13_MASK 0xFFu 212 #define S32_NVIC_IP_PRI13_SHIFT 0u 213 #define S32_NVIC_IP_PRI13_WIDTH 8u 214 #define S32_NVIC_IP_PRI13(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI13_SHIFT))&S32_NVIC_IP_PRI13_MASK) 215 #define S32_NVIC_IP_PRI14_MASK 0xFFu 216 #define S32_NVIC_IP_PRI14_SHIFT 0u 217 #define S32_NVIC_IP_PRI14_WIDTH 8u 218 #define S32_NVIC_IP_PRI14(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI14_SHIFT))&S32_NVIC_IP_PRI14_MASK) 219 #define S32_NVIC_IP_PRI15_MASK 0xFFu 220 #define S32_NVIC_IP_PRI15_SHIFT 0u 221 #define S32_NVIC_IP_PRI15_WIDTH 8u 222 #define S32_NVIC_IP_PRI15(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI15_SHIFT))&S32_NVIC_IP_PRI15_MASK) 223 #define S32_NVIC_IP_PRI16_MASK 0xFFu 224 #define S32_NVIC_IP_PRI16_SHIFT 0u 225 #define S32_NVIC_IP_PRI16_WIDTH 8u 226 #define S32_NVIC_IP_PRI16(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI16_SHIFT))&S32_NVIC_IP_PRI16_MASK) 227 #define S32_NVIC_IP_PRI17_MASK 0xFFu 228 #define S32_NVIC_IP_PRI17_SHIFT 0u 229 #define S32_NVIC_IP_PRI17_WIDTH 8u 230 #define S32_NVIC_IP_PRI17(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI17_SHIFT))&S32_NVIC_IP_PRI17_MASK) 231 #define S32_NVIC_IP_PRI18_MASK 0xFFu 232 #define S32_NVIC_IP_PRI18_SHIFT 0u 233 #define S32_NVIC_IP_PRI18_WIDTH 8u 234 #define S32_NVIC_IP_PRI18(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI18_SHIFT))&S32_NVIC_IP_PRI18_MASK) 235 #define S32_NVIC_IP_PRI19_MASK 0xFFu 236 #define S32_NVIC_IP_PRI19_SHIFT 0u 237 #define S32_NVIC_IP_PRI19_WIDTH 8u 238 #define S32_NVIC_IP_PRI19(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI19_SHIFT))&S32_NVIC_IP_PRI19_MASK) 239 #define S32_NVIC_IP_PRI20_MASK 0xFFu 240 #define S32_NVIC_IP_PRI20_SHIFT 0u 241 #define S32_NVIC_IP_PRI20_WIDTH 8u 242 #define S32_NVIC_IP_PRI20(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI20_SHIFT))&S32_NVIC_IP_PRI20_MASK) 243 #define S32_NVIC_IP_PRI21_MASK 0xFFu 244 #define S32_NVIC_IP_PRI21_SHIFT 0u 245 #define S32_NVIC_IP_PRI21_WIDTH 8u 246 #define S32_NVIC_IP_PRI21(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI21_SHIFT))&S32_NVIC_IP_PRI21_MASK) 247 #define S32_NVIC_IP_PRI22_MASK 0xFFu 248 #define S32_NVIC_IP_PRI22_SHIFT 0u 249 #define S32_NVIC_IP_PRI22_WIDTH 8u 250 #define S32_NVIC_IP_PRI22(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI22_SHIFT))&S32_NVIC_IP_PRI22_MASK) 251 #define S32_NVIC_IP_PRI23_MASK 0xFFu 252 #define S32_NVIC_IP_PRI23_SHIFT 0u 253 #define S32_NVIC_IP_PRI23_WIDTH 8u 254 #define S32_NVIC_IP_PRI23(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI23_SHIFT))&S32_NVIC_IP_PRI23_MASK) 255 #define S32_NVIC_IP_PRI24_MASK 0xFFu 256 #define S32_NVIC_IP_PRI24_SHIFT 0u 257 #define S32_NVIC_IP_PRI24_WIDTH 8u 258 #define S32_NVIC_IP_PRI24(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI24_SHIFT))&S32_NVIC_IP_PRI24_MASK) 259 #define S32_NVIC_IP_PRI25_MASK 0xFFu 260 #define S32_NVIC_IP_PRI25_SHIFT 0u 261 #define S32_NVIC_IP_PRI25_WIDTH 8u 262 #define S32_NVIC_IP_PRI25(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI25_SHIFT))&S32_NVIC_IP_PRI25_MASK) 263 #define S32_NVIC_IP_PRI26_MASK 0xFFu 264 #define S32_NVIC_IP_PRI26_SHIFT 0u 265 #define S32_NVIC_IP_PRI26_WIDTH 8u 266 #define S32_NVIC_IP_PRI26(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI26_SHIFT))&S32_NVIC_IP_PRI26_MASK) 267 #define S32_NVIC_IP_PRI27_MASK 0xFFu 268 #define S32_NVIC_IP_PRI27_SHIFT 0u 269 #define S32_NVIC_IP_PRI27_WIDTH 8u 270 #define S32_NVIC_IP_PRI27(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI27_SHIFT))&S32_NVIC_IP_PRI27_MASK) 271 #define S32_NVIC_IP_PRI28_MASK 0xFFu 272 #define S32_NVIC_IP_PRI28_SHIFT 0u 273 #define S32_NVIC_IP_PRI28_WIDTH 8u 274 #define S32_NVIC_IP_PRI28(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI28_SHIFT))&S32_NVIC_IP_PRI28_MASK) 275 #define S32_NVIC_IP_PRI29_MASK 0xFFu 276 #define S32_NVIC_IP_PRI29_SHIFT 0u 277 #define S32_NVIC_IP_PRI29_WIDTH 8u 278 #define S32_NVIC_IP_PRI29(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI29_SHIFT))&S32_NVIC_IP_PRI29_MASK) 279 #define S32_NVIC_IP_PRI30_MASK 0xFFu 280 #define S32_NVIC_IP_PRI30_SHIFT 0u 281 #define S32_NVIC_IP_PRI30_WIDTH 8u 282 #define S32_NVIC_IP_PRI30(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI30_SHIFT))&S32_NVIC_IP_PRI30_MASK) 283 #define S32_NVIC_IP_PRI31_MASK 0xFFu 284 #define S32_NVIC_IP_PRI31_SHIFT 0u 285 #define S32_NVIC_IP_PRI31_WIDTH 8u 286 #define S32_NVIC_IP_PRI31(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI31_SHIFT))&S32_NVIC_IP_PRI31_MASK) 287 #define S32_NVIC_IP_PRI32_MASK 0xFFu 288 #define S32_NVIC_IP_PRI32_SHIFT 0u 289 #define S32_NVIC_IP_PRI32_WIDTH 8u 290 #define S32_NVIC_IP_PRI32(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI32_SHIFT))&S32_NVIC_IP_PRI32_MASK) 291 #define S32_NVIC_IP_PRI33_MASK 0xFFu 292 #define S32_NVIC_IP_PRI33_SHIFT 0u 293 #define S32_NVIC_IP_PRI33_WIDTH 8u 294 #define S32_NVIC_IP_PRI33(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI33_SHIFT))&S32_NVIC_IP_PRI33_MASK) 295 #define S32_NVIC_IP_PRI34_MASK 0xFFu 296 #define S32_NVIC_IP_PRI34_SHIFT 0u 297 #define S32_NVIC_IP_PRI34_WIDTH 8u 298 #define S32_NVIC_IP_PRI34(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI34_SHIFT))&S32_NVIC_IP_PRI34_MASK) 299 #define S32_NVIC_IP_PRI35_MASK 0xFFu 300 #define S32_NVIC_IP_PRI35_SHIFT 0u 301 #define S32_NVIC_IP_PRI35_WIDTH 8u 302 #define S32_NVIC_IP_PRI35(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI35_SHIFT))&S32_NVIC_IP_PRI35_MASK) 303 #define S32_NVIC_IP_PRI36_MASK 0xFFu 304 #define S32_NVIC_IP_PRI36_SHIFT 0u 305 #define S32_NVIC_IP_PRI36_WIDTH 8u 306 #define S32_NVIC_IP_PRI36(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI36_SHIFT))&S32_NVIC_IP_PRI36_MASK) 307 #define S32_NVIC_IP_PRI37_MASK 0xFFu 308 #define S32_NVIC_IP_PRI37_SHIFT 0u 309 #define S32_NVIC_IP_PRI37_WIDTH 8u 310 #define S32_NVIC_IP_PRI37(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI37_SHIFT))&S32_NVIC_IP_PRI37_MASK) 311 #define S32_NVIC_IP_PRI38_MASK 0xFFu 312 #define S32_NVIC_IP_PRI38_SHIFT 0u 313 #define S32_NVIC_IP_PRI38_WIDTH 8u 314 #define S32_NVIC_IP_PRI38(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI38_SHIFT))&S32_NVIC_IP_PRI38_MASK) 315 #define S32_NVIC_IP_PRI39_MASK 0xFFu 316 #define S32_NVIC_IP_PRI39_SHIFT 0u 317 #define S32_NVIC_IP_PRI39_WIDTH 8u 318 #define S32_NVIC_IP_PRI39(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI39_SHIFT))&S32_NVIC_IP_PRI39_MASK) 319 #define S32_NVIC_IP_PRI40_MASK 0xFFu 320 #define S32_NVIC_IP_PRI40_SHIFT 0u 321 #define S32_NVIC_IP_PRI40_WIDTH 8u 322 #define S32_NVIC_IP_PRI40(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI40_SHIFT))&S32_NVIC_IP_PRI40_MASK) 323 #define S32_NVIC_IP_PRI41_MASK 0xFFu 324 #define S32_NVIC_IP_PRI41_SHIFT 0u 325 #define S32_NVIC_IP_PRI41_WIDTH 8u 326 #define S32_NVIC_IP_PRI41(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI41_SHIFT))&S32_NVIC_IP_PRI41_MASK) 327 #define S32_NVIC_IP_PRI42_MASK 0xFFu 328 #define S32_NVIC_IP_PRI42_SHIFT 0u 329 #define S32_NVIC_IP_PRI42_WIDTH 8u 330 #define S32_NVIC_IP_PRI42(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI42_SHIFT))&S32_NVIC_IP_PRI42_MASK) 331 #define S32_NVIC_IP_PRI43_MASK 0xFFu 332 #define S32_NVIC_IP_PRI43_SHIFT 0u 333 #define S32_NVIC_IP_PRI43_WIDTH 8u 334 #define S32_NVIC_IP_PRI43(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI43_SHIFT))&S32_NVIC_IP_PRI43_MASK) 335 #define S32_NVIC_IP_PRI44_MASK 0xFFu 336 #define S32_NVIC_IP_PRI44_SHIFT 0u 337 #define S32_NVIC_IP_PRI44_WIDTH 8u 338 #define S32_NVIC_IP_PRI44(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI44_SHIFT))&S32_NVIC_IP_PRI44_MASK) 339 #define S32_NVIC_IP_PRI45_MASK 0xFFu 340 #define S32_NVIC_IP_PRI45_SHIFT 0u 341 #define S32_NVIC_IP_PRI45_WIDTH 8u 342 #define S32_NVIC_IP_PRI45(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI45_SHIFT))&S32_NVIC_IP_PRI45_MASK) 343 #define S32_NVIC_IP_PRI46_MASK 0xFFu 344 #define S32_NVIC_IP_PRI46_SHIFT 0u 345 #define S32_NVIC_IP_PRI46_WIDTH 8u 346 #define S32_NVIC_IP_PRI46(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI46_SHIFT))&S32_NVIC_IP_PRI46_MASK) 347 #define S32_NVIC_IP_PRI47_MASK 0xFFu 348 #define S32_NVIC_IP_PRI47_SHIFT 0u 349 #define S32_NVIC_IP_PRI47_WIDTH 8u 350 #define S32_NVIC_IP_PRI47(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI47_SHIFT))&S32_NVIC_IP_PRI47_MASK) 351 #define S32_NVIC_IP_PRI48_MASK 0xFFu 352 #define S32_NVIC_IP_PRI48_SHIFT 0u 353 #define S32_NVIC_IP_PRI48_WIDTH 8u 354 #define S32_NVIC_IP_PRI48(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI48_SHIFT))&S32_NVIC_IP_PRI48_MASK) 355 #define S32_NVIC_IP_PRI49_MASK 0xFFu 356 #define S32_NVIC_IP_PRI49_SHIFT 0u 357 #define S32_NVIC_IP_PRI49_WIDTH 8u 358 #define S32_NVIC_IP_PRI49(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI49_SHIFT))&S32_NVIC_IP_PRI49_MASK) 359 #define S32_NVIC_IP_PRI50_MASK 0xFFu 360 #define S32_NVIC_IP_PRI50_SHIFT 0u 361 #define S32_NVIC_IP_PRI50_WIDTH 8u 362 #define S32_NVIC_IP_PRI50(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI50_SHIFT))&S32_NVIC_IP_PRI50_MASK) 363 #define S32_NVIC_IP_PRI51_MASK 0xFFu 364 #define S32_NVIC_IP_PRI51_SHIFT 0u 365 #define S32_NVIC_IP_PRI51_WIDTH 8u 366 #define S32_NVIC_IP_PRI51(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI51_SHIFT))&S32_NVIC_IP_PRI51_MASK) 367 #define S32_NVIC_IP_PRI52_MASK 0xFFu 368 #define S32_NVIC_IP_PRI52_SHIFT 0u 369 #define S32_NVIC_IP_PRI52_WIDTH 8u 370 #define S32_NVIC_IP_PRI52(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI52_SHIFT))&S32_NVIC_IP_PRI52_MASK) 371 #define S32_NVIC_IP_PRI53_MASK 0xFFu 372 #define S32_NVIC_IP_PRI53_SHIFT 0u 373 #define S32_NVIC_IP_PRI53_WIDTH 8u 374 #define S32_NVIC_IP_PRI53(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI53_SHIFT))&S32_NVIC_IP_PRI53_MASK) 375 #define S32_NVIC_IP_PRI54_MASK 0xFFu 376 #define S32_NVIC_IP_PRI54_SHIFT 0u 377 #define S32_NVIC_IP_PRI54_WIDTH 8u 378 #define S32_NVIC_IP_PRI54(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI54_SHIFT))&S32_NVIC_IP_PRI54_MASK) 379 #define S32_NVIC_IP_PRI55_MASK 0xFFu 380 #define S32_NVIC_IP_PRI55_SHIFT 0u 381 #define S32_NVIC_IP_PRI55_WIDTH 8u 382 #define S32_NVIC_IP_PRI55(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI55_SHIFT))&S32_NVIC_IP_PRI55_MASK) 383 #define S32_NVIC_IP_PRI56_MASK 0xFFu 384 #define S32_NVIC_IP_PRI56_SHIFT 0u 385 #define S32_NVIC_IP_PRI56_WIDTH 8u 386 #define S32_NVIC_IP_PRI56(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI56_SHIFT))&S32_NVIC_IP_PRI56_MASK) 387 #define S32_NVIC_IP_PRI57_MASK 0xFFu 388 #define S32_NVIC_IP_PRI57_SHIFT 0u 389 #define S32_NVIC_IP_PRI57_WIDTH 8u 390 #define S32_NVIC_IP_PRI57(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI57_SHIFT))&S32_NVIC_IP_PRI57_MASK) 391 #define S32_NVIC_IP_PRI58_MASK 0xFFu 392 #define S32_NVIC_IP_PRI58_SHIFT 0u 393 #define S32_NVIC_IP_PRI58_WIDTH 8u 394 #define S32_NVIC_IP_PRI58(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI58_SHIFT))&S32_NVIC_IP_PRI58_MASK) 395 #define S32_NVIC_IP_PRI59_MASK 0xFFu 396 #define S32_NVIC_IP_PRI59_SHIFT 0u 397 #define S32_NVIC_IP_PRI59_WIDTH 8u 398 #define S32_NVIC_IP_PRI59(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI59_SHIFT))&S32_NVIC_IP_PRI59_MASK) 399 #define S32_NVIC_IP_PRI60_MASK 0xFFu 400 #define S32_NVIC_IP_PRI60_SHIFT 0u 401 #define S32_NVIC_IP_PRI60_WIDTH 8u 402 #define S32_NVIC_IP_PRI60(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI60_SHIFT))&S32_NVIC_IP_PRI60_MASK) 403 #define S32_NVIC_IP_PRI61_MASK 0xFFu 404 #define S32_NVIC_IP_PRI61_SHIFT 0u 405 #define S32_NVIC_IP_PRI61_WIDTH 8u 406 #define S32_NVIC_IP_PRI61(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI61_SHIFT))&S32_NVIC_IP_PRI61_MASK) 407 #define S32_NVIC_IP_PRI62_MASK 0xFFu 408 #define S32_NVIC_IP_PRI62_SHIFT 0u 409 #define S32_NVIC_IP_PRI62_WIDTH 8u 410 #define S32_NVIC_IP_PRI62(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI62_SHIFT))&S32_NVIC_IP_PRI62_MASK) 411 #define S32_NVIC_IP_PRI63_MASK 0xFFu 412 #define S32_NVIC_IP_PRI63_SHIFT 0u 413 #define S32_NVIC_IP_PRI63_WIDTH 8u 414 #define S32_NVIC_IP_PRI63(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI63_SHIFT))&S32_NVIC_IP_PRI63_MASK) 415 #define S32_NVIC_IP_PRI64_MASK 0xFFu 416 #define S32_NVIC_IP_PRI64_SHIFT 0u 417 #define S32_NVIC_IP_PRI64_WIDTH 8u 418 #define S32_NVIC_IP_PRI64(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI64_SHIFT))&S32_NVIC_IP_PRI64_MASK) 419 #define S32_NVIC_IP_PRI65_MASK 0xFFu 420 #define S32_NVIC_IP_PRI65_SHIFT 0u 421 #define S32_NVIC_IP_PRI65_WIDTH 8u 422 #define S32_NVIC_IP_PRI65(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI65_SHIFT))&S32_NVIC_IP_PRI65_MASK) 423 #define S32_NVIC_IP_PRI66_MASK 0xFFu 424 #define S32_NVIC_IP_PRI66_SHIFT 0u 425 #define S32_NVIC_IP_PRI66_WIDTH 8u 426 #define S32_NVIC_IP_PRI66(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI66_SHIFT))&S32_NVIC_IP_PRI66_MASK) 427 #define S32_NVIC_IP_PRI67_MASK 0xFFu 428 #define S32_NVIC_IP_PRI67_SHIFT 0u 429 #define S32_NVIC_IP_PRI67_WIDTH 8u 430 #define S32_NVIC_IP_PRI67(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI67_SHIFT))&S32_NVIC_IP_PRI67_MASK) 431 #define S32_NVIC_IP_PRI68_MASK 0xFFu 432 #define S32_NVIC_IP_PRI68_SHIFT 0u 433 #define S32_NVIC_IP_PRI68_WIDTH 8u 434 #define S32_NVIC_IP_PRI68(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI68_SHIFT))&S32_NVIC_IP_PRI68_MASK) 435 #define S32_NVIC_IP_PRI69_MASK 0xFFu 436 #define S32_NVIC_IP_PRI69_SHIFT 0u 437 #define S32_NVIC_IP_PRI69_WIDTH 8u 438 #define S32_NVIC_IP_PRI69(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI69_SHIFT))&S32_NVIC_IP_PRI69_MASK) 439 #define S32_NVIC_IP_PRI70_MASK 0xFFu 440 #define S32_NVIC_IP_PRI70_SHIFT 0u 441 #define S32_NVIC_IP_PRI70_WIDTH 8u 442 #define S32_NVIC_IP_PRI70(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI70_SHIFT))&S32_NVIC_IP_PRI70_MASK) 443 #define S32_NVIC_IP_PRI71_MASK 0xFFu 444 #define S32_NVIC_IP_PRI71_SHIFT 0u 445 #define S32_NVIC_IP_PRI71_WIDTH 8u 446 #define S32_NVIC_IP_PRI71(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI71_SHIFT))&S32_NVIC_IP_PRI71_MASK) 447 #define S32_NVIC_IP_PRI72_MASK 0xFFu 448 #define S32_NVIC_IP_PRI72_SHIFT 0u 449 #define S32_NVIC_IP_PRI72_WIDTH 8u 450 #define S32_NVIC_IP_PRI72(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI72_SHIFT))&S32_NVIC_IP_PRI72_MASK) 451 #define S32_NVIC_IP_PRI73_MASK 0xFFu 452 #define S32_NVIC_IP_PRI73_SHIFT 0u 453 #define S32_NVIC_IP_PRI73_WIDTH 8u 454 #define S32_NVIC_IP_PRI73(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI73_SHIFT))&S32_NVIC_IP_PRI73_MASK) 455 #define S32_NVIC_IP_PRI74_MASK 0xFFu 456 #define S32_NVIC_IP_PRI74_SHIFT 0u 457 #define S32_NVIC_IP_PRI74_WIDTH 8u 458 #define S32_NVIC_IP_PRI74(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI74_SHIFT))&S32_NVIC_IP_PRI74_MASK) 459 #define S32_NVIC_IP_PRI75_MASK 0xFFu 460 #define S32_NVIC_IP_PRI75_SHIFT 0u 461 #define S32_NVIC_IP_PRI75_WIDTH 8u 462 #define S32_NVIC_IP_PRI75(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI75_SHIFT))&S32_NVIC_IP_PRI75_MASK) 463 #define S32_NVIC_IP_PRI76_MASK 0xFFu 464 #define S32_NVIC_IP_PRI76_SHIFT 0u 465 #define S32_NVIC_IP_PRI76_WIDTH 8u 466 #define S32_NVIC_IP_PRI76(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI76_SHIFT))&S32_NVIC_IP_PRI76_MASK) 467 #define S32_NVIC_IP_PRI77_MASK 0xFFu 468 #define S32_NVIC_IP_PRI77_SHIFT 0u 469 #define S32_NVIC_IP_PRI77_WIDTH 8u 470 #define S32_NVIC_IP_PRI77(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI77_SHIFT))&S32_NVIC_IP_PRI77_MASK) 471 #define S32_NVIC_IP_PRI78_MASK 0xFFu 472 #define S32_NVIC_IP_PRI78_SHIFT 0u 473 #define S32_NVIC_IP_PRI78_WIDTH 8u 474 #define S32_NVIC_IP_PRI78(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI78_SHIFT))&S32_NVIC_IP_PRI78_MASK) 475 #define S32_NVIC_IP_PRI79_MASK 0xFFu 476 #define S32_NVIC_IP_PRI79_SHIFT 0u 477 #define S32_NVIC_IP_PRI79_WIDTH 8u 478 #define S32_NVIC_IP_PRI79(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI79_SHIFT))&S32_NVIC_IP_PRI79_MASK) 479 #define S32_NVIC_IP_PRI80_MASK 0xFFu 480 #define S32_NVIC_IP_PRI80_SHIFT 0u 481 #define S32_NVIC_IP_PRI80_WIDTH 8u 482 #define S32_NVIC_IP_PRI80(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI80_SHIFT))&S32_NVIC_IP_PRI80_MASK) 483 #define S32_NVIC_IP_PRI81_MASK 0xFFu 484 #define S32_NVIC_IP_PRI81_SHIFT 0u 485 #define S32_NVIC_IP_PRI81_WIDTH 8u 486 #define S32_NVIC_IP_PRI81(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI81_SHIFT))&S32_NVIC_IP_PRI81_MASK) 487 #define S32_NVIC_IP_PRI82_MASK 0xFFu 488 #define S32_NVIC_IP_PRI82_SHIFT 0u 489 #define S32_NVIC_IP_PRI82_WIDTH 8u 490 #define S32_NVIC_IP_PRI82(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI82_SHIFT))&S32_NVIC_IP_PRI82_MASK) 491 #define S32_NVIC_IP_PRI83_MASK 0xFFu 492 #define S32_NVIC_IP_PRI83_SHIFT 0u 493 #define S32_NVIC_IP_PRI83_WIDTH 8u 494 #define S32_NVIC_IP_PRI83(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI83_SHIFT))&S32_NVIC_IP_PRI83_MASK) 495 #define S32_NVIC_IP_PRI84_MASK 0xFFu 496 #define S32_NVIC_IP_PRI84_SHIFT 0u 497 #define S32_NVIC_IP_PRI84_WIDTH 8u 498 #define S32_NVIC_IP_PRI84(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI84_SHIFT))&S32_NVIC_IP_PRI84_MASK) 499 #define S32_NVIC_IP_PRI85_MASK 0xFFu 500 #define S32_NVIC_IP_PRI85_SHIFT 0u 501 #define S32_NVIC_IP_PRI85_WIDTH 8u 502 #define S32_NVIC_IP_PRI85(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI85_SHIFT))&S32_NVIC_IP_PRI85_MASK) 503 #define S32_NVIC_IP_PRI86_MASK 0xFFu 504 #define S32_NVIC_IP_PRI86_SHIFT 0u 505 #define S32_NVIC_IP_PRI86_WIDTH 8u 506 #define S32_NVIC_IP_PRI86(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI86_SHIFT))&S32_NVIC_IP_PRI86_MASK) 507 #define S32_NVIC_IP_PRI87_MASK 0xFFu 508 #define S32_NVIC_IP_PRI87_SHIFT 0u 509 #define S32_NVIC_IP_PRI87_WIDTH 8u 510 #define S32_NVIC_IP_PRI87(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI87_SHIFT))&S32_NVIC_IP_PRI87_MASK) 511 #define S32_NVIC_IP_PRI88_MASK 0xFFu 512 #define S32_NVIC_IP_PRI88_SHIFT 0u 513 #define S32_NVIC_IP_PRI88_WIDTH 8u 514 #define S32_NVIC_IP_PRI88(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI88_SHIFT))&S32_NVIC_IP_PRI88_MASK) 515 #define S32_NVIC_IP_PRI89_MASK 0xFFu 516 #define S32_NVIC_IP_PRI89_SHIFT 0u 517 #define S32_NVIC_IP_PRI89_WIDTH 8u 518 #define S32_NVIC_IP_PRI89(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI89_SHIFT))&S32_NVIC_IP_PRI89_MASK) 519 #define S32_NVIC_IP_PRI90_MASK 0xFFu 520 #define S32_NVIC_IP_PRI90_SHIFT 0u 521 #define S32_NVIC_IP_PRI90_WIDTH 8u 522 #define S32_NVIC_IP_PRI90(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI90_SHIFT))&S32_NVIC_IP_PRI90_MASK) 523 #define S32_NVIC_IP_PRI91_MASK 0xFFu 524 #define S32_NVIC_IP_PRI91_SHIFT 0u 525 #define S32_NVIC_IP_PRI91_WIDTH 8u 526 #define S32_NVIC_IP_PRI91(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI91_SHIFT))&S32_NVIC_IP_PRI91_MASK) 527 #define S32_NVIC_IP_PRI92_MASK 0xFFu 528 #define S32_NVIC_IP_PRI92_SHIFT 0u 529 #define S32_NVIC_IP_PRI92_WIDTH 8u 530 #define S32_NVIC_IP_PRI92(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI92_SHIFT))&S32_NVIC_IP_PRI92_MASK) 531 #define S32_NVIC_IP_PRI93_MASK 0xFFu 532 #define S32_NVIC_IP_PRI93_SHIFT 0u 533 #define S32_NVIC_IP_PRI93_WIDTH 8u 534 #define S32_NVIC_IP_PRI93(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI93_SHIFT))&S32_NVIC_IP_PRI93_MASK) 535 #define S32_NVIC_IP_PRI94_MASK 0xFFu 536 #define S32_NVIC_IP_PRI94_SHIFT 0u 537 #define S32_NVIC_IP_PRI94_WIDTH 8u 538 #define S32_NVIC_IP_PRI94(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI94_SHIFT))&S32_NVIC_IP_PRI94_MASK) 539 #define S32_NVIC_IP_PRI95_MASK 0xFFu 540 #define S32_NVIC_IP_PRI95_SHIFT 0u 541 #define S32_NVIC_IP_PRI95_WIDTH 8u 542 #define S32_NVIC_IP_PRI95(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI95_SHIFT))&S32_NVIC_IP_PRI95_MASK) 543 #define S32_NVIC_IP_PRI96_MASK 0xFFu 544 #define S32_NVIC_IP_PRI96_SHIFT 0u 545 #define S32_NVIC_IP_PRI96_WIDTH 8u 546 #define S32_NVIC_IP_PRI96(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI96_SHIFT))&S32_NVIC_IP_PRI96_MASK) 547 #define S32_NVIC_IP_PRI97_MASK 0xFFu 548 #define S32_NVIC_IP_PRI97_SHIFT 0u 549 #define S32_NVIC_IP_PRI97_WIDTH 8u 550 #define S32_NVIC_IP_PRI97(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI97_SHIFT))&S32_NVIC_IP_PRI97_MASK) 551 #define S32_NVIC_IP_PRI98_MASK 0xFFu 552 #define S32_NVIC_IP_PRI98_SHIFT 0u 553 #define S32_NVIC_IP_PRI98_WIDTH 8u 554 #define S32_NVIC_IP_PRI98(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI98_SHIFT))&S32_NVIC_IP_PRI98_MASK) 555 #define S32_NVIC_IP_PRI99_MASK 0xFFu 556 #define S32_NVIC_IP_PRI99_SHIFT 0u 557 #define S32_NVIC_IP_PRI99_WIDTH 8u 558 #define S32_NVIC_IP_PRI99(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI99_SHIFT))&S32_NVIC_IP_PRI99_MASK) 559 #define S32_NVIC_IP_PRI100_MASK 0xFFu 560 #define S32_NVIC_IP_PRI100_SHIFT 0u 561 #define S32_NVIC_IP_PRI100_WIDTH 8u 562 #define S32_NVIC_IP_PRI100(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI100_SHIFT))&S32_NVIC_IP_PRI100_MASK) 563 #define S32_NVIC_IP_PRI101_MASK 0xFFu 564 #define S32_NVIC_IP_PRI101_SHIFT 0u 565 #define S32_NVIC_IP_PRI101_WIDTH 8u 566 #define S32_NVIC_IP_PRI101(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI101_SHIFT))&S32_NVIC_IP_PRI101_MASK) 567 #define S32_NVIC_IP_PRI102_MASK 0xFFu 568 #define S32_NVIC_IP_PRI102_SHIFT 0u 569 #define S32_NVIC_IP_PRI102_WIDTH 8u 570 #define S32_NVIC_IP_PRI102(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI102_SHIFT))&S32_NVIC_IP_PRI102_MASK) 571 #define S32_NVIC_IP_PRI103_MASK 0xFFu 572 #define S32_NVIC_IP_PRI103_SHIFT 0u 573 #define S32_NVIC_IP_PRI103_WIDTH 8u 574 #define S32_NVIC_IP_PRI103(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI103_SHIFT))&S32_NVIC_IP_PRI103_MASK) 575 #define S32_NVIC_IP_PRI104_MASK 0xFFu 576 #define S32_NVIC_IP_PRI104_SHIFT 0u 577 #define S32_NVIC_IP_PRI104_WIDTH 8u 578 #define S32_NVIC_IP_PRI104(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI104_SHIFT))&S32_NVIC_IP_PRI104_MASK) 579 #define S32_NVIC_IP_PRI105_MASK 0xFFu 580 #define S32_NVIC_IP_PRI105_SHIFT 0u 581 #define S32_NVIC_IP_PRI105_WIDTH 8u 582 #define S32_NVIC_IP_PRI105(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI105_SHIFT))&S32_NVIC_IP_PRI105_MASK) 583 #define S32_NVIC_IP_PRI106_MASK 0xFFu 584 #define S32_NVIC_IP_PRI106_SHIFT 0u 585 #define S32_NVIC_IP_PRI106_WIDTH 8u 586 #define S32_NVIC_IP_PRI106(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI106_SHIFT))&S32_NVIC_IP_PRI106_MASK) 587 #define S32_NVIC_IP_PRI107_MASK 0xFFu 588 #define S32_NVIC_IP_PRI107_SHIFT 0u 589 #define S32_NVIC_IP_PRI107_WIDTH 8u 590 #define S32_NVIC_IP_PRI107(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI107_SHIFT))&S32_NVIC_IP_PRI107_MASK) 591 #define S32_NVIC_IP_PRI108_MASK 0xFFu 592 #define S32_NVIC_IP_PRI108_SHIFT 0u 593 #define S32_NVIC_IP_PRI108_WIDTH 8u 594 #define S32_NVIC_IP_PRI108(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI108_SHIFT))&S32_NVIC_IP_PRI108_MASK) 595 #define S32_NVIC_IP_PRI109_MASK 0xFFu 596 #define S32_NVIC_IP_PRI109_SHIFT 0u 597 #define S32_NVIC_IP_PRI109_WIDTH 8u 598 #define S32_NVIC_IP_PRI109(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI109_SHIFT))&S32_NVIC_IP_PRI109_MASK) 599 #define S32_NVIC_IP_PRI110_MASK 0xFFu 600 #define S32_NVIC_IP_PRI110_SHIFT 0u 601 #define S32_NVIC_IP_PRI110_WIDTH 8u 602 #define S32_NVIC_IP_PRI110(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI110_SHIFT))&S32_NVIC_IP_PRI110_MASK) 603 #define S32_NVIC_IP_PRI111_MASK 0xFFu 604 #define S32_NVIC_IP_PRI111_SHIFT 0u 605 #define S32_NVIC_IP_PRI111_WIDTH 8u 606 #define S32_NVIC_IP_PRI111(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI111_SHIFT))&S32_NVIC_IP_PRI111_MASK) 607 #define S32_NVIC_IP_PRI112_MASK 0xFFu 608 #define S32_NVIC_IP_PRI112_SHIFT 0u 609 #define S32_NVIC_IP_PRI112_WIDTH 8u 610 #define S32_NVIC_IP_PRI112(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI112_SHIFT))&S32_NVIC_IP_PRI112_MASK) 611 #define S32_NVIC_IP_PRI113_MASK 0xFFu 612 #define S32_NVIC_IP_PRI113_SHIFT 0u 613 #define S32_NVIC_IP_PRI113_WIDTH 8u 614 #define S32_NVIC_IP_PRI113(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI113_SHIFT))&S32_NVIC_IP_PRI113_MASK) 615 #define S32_NVIC_IP_PRI114_MASK 0xFFu 616 #define S32_NVIC_IP_PRI114_SHIFT 0u 617 #define S32_NVIC_IP_PRI114_WIDTH 8u 618 #define S32_NVIC_IP_PRI114(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI114_SHIFT))&S32_NVIC_IP_PRI114_MASK) 619 #define S32_NVIC_IP_PRI115_MASK 0xFFu 620 #define S32_NVIC_IP_PRI115_SHIFT 0u 621 #define S32_NVIC_IP_PRI115_WIDTH 8u 622 #define S32_NVIC_IP_PRI115(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI115_SHIFT))&S32_NVIC_IP_PRI115_MASK) 623 #define S32_NVIC_IP_PRI116_MASK 0xFFu 624 #define S32_NVIC_IP_PRI116_SHIFT 0u 625 #define S32_NVIC_IP_PRI116_WIDTH 8u 626 #define S32_NVIC_IP_PRI116(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI116_SHIFT))&S32_NVIC_IP_PRI116_MASK) 627 #define S32_NVIC_IP_PRI117_MASK 0xFFu 628 #define S32_NVIC_IP_PRI117_SHIFT 0u 629 #define S32_NVIC_IP_PRI117_WIDTH 8u 630 #define S32_NVIC_IP_PRI117(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI117_SHIFT))&S32_NVIC_IP_PRI117_MASK) 631 #define S32_NVIC_IP_PRI118_MASK 0xFFu 632 #define S32_NVIC_IP_PRI118_SHIFT 0u 633 #define S32_NVIC_IP_PRI118_WIDTH 8u 634 #define S32_NVIC_IP_PRI118(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI118_SHIFT))&S32_NVIC_IP_PRI118_MASK) 635 #define S32_NVIC_IP_PRI119_MASK 0xFFu 636 #define S32_NVIC_IP_PRI119_SHIFT 0u 637 #define S32_NVIC_IP_PRI119_WIDTH 8u 638 #define S32_NVIC_IP_PRI119(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI119_SHIFT))&S32_NVIC_IP_PRI119_MASK) 639 #define S32_NVIC_IP_PRI120_MASK 0xFFu 640 #define S32_NVIC_IP_PRI120_SHIFT 0u 641 #define S32_NVIC_IP_PRI120_WIDTH 8u 642 #define S32_NVIC_IP_PRI120(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI120_SHIFT))&S32_NVIC_IP_PRI120_MASK) 643 #define S32_NVIC_IP_PRI121_MASK 0xFFu 644 #define S32_NVIC_IP_PRI121_SHIFT 0u 645 #define S32_NVIC_IP_PRI121_WIDTH 8u 646 #define S32_NVIC_IP_PRI121(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI121_SHIFT))&S32_NVIC_IP_PRI121_MASK) 647 #define S32_NVIC_IP_PRI122_MASK 0xFFu 648 #define S32_NVIC_IP_PRI122_SHIFT 0u 649 #define S32_NVIC_IP_PRI122_WIDTH 8u 650 #define S32_NVIC_IP_PRI122(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI122_SHIFT))&S32_NVIC_IP_PRI122_MASK) 651 #define S32_NVIC_IP_PRI123_MASK 0xFFu 652 #define S32_NVIC_IP_PRI123_SHIFT 0u 653 #define S32_NVIC_IP_PRI123_WIDTH 8u 654 #define S32_NVIC_IP_PRI123(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI123_SHIFT))&S32_NVIC_IP_PRI123_MASK) 655 #define S32_NVIC_IP_PRI124_MASK 0xFFu 656 #define S32_NVIC_IP_PRI124_SHIFT 0u 657 #define S32_NVIC_IP_PRI124_WIDTH 8u 658 #define S32_NVIC_IP_PRI124(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI124_SHIFT))&S32_NVIC_IP_PRI124_MASK) 659 #define S32_NVIC_IP_PRI125_MASK 0xFFu 660 #define S32_NVIC_IP_PRI125_SHIFT 0u 661 #define S32_NVIC_IP_PRI125_WIDTH 8u 662 #define S32_NVIC_IP_PRI125(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI125_SHIFT))&S32_NVIC_IP_PRI125_MASK) 663 #define S32_NVIC_IP_PRI126_MASK 0xFFu 664 #define S32_NVIC_IP_PRI126_SHIFT 0u 665 #define S32_NVIC_IP_PRI126_WIDTH 8u 666 #define S32_NVIC_IP_PRI126(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI126_SHIFT))&S32_NVIC_IP_PRI126_MASK) 667 #define S32_NVIC_IP_PRI127_MASK 0xFFu 668 #define S32_NVIC_IP_PRI127_SHIFT 0u 669 #define S32_NVIC_IP_PRI127_WIDTH 8u 670 #define S32_NVIC_IP_PRI127(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI127_SHIFT))&S32_NVIC_IP_PRI127_MASK) 671 #define S32_NVIC_IP_PRI128_MASK 0xFFu 672 #define S32_NVIC_IP_PRI128_SHIFT 0u 673 #define S32_NVIC_IP_PRI128_WIDTH 8u 674 #define S32_NVIC_IP_PRI128(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI128_SHIFT))&S32_NVIC_IP_PRI128_MASK) 675 #define S32_NVIC_IP_PRI129_MASK 0xFFu 676 #define S32_NVIC_IP_PRI129_SHIFT 0u 677 #define S32_NVIC_IP_PRI129_WIDTH 8u 678 #define S32_NVIC_IP_PRI129(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI129_SHIFT))&S32_NVIC_IP_PRI129_MASK) 679 #define S32_NVIC_IP_PRI130_MASK 0xFFu 680 #define S32_NVIC_IP_PRI130_SHIFT 0u 681 #define S32_NVIC_IP_PRI130_WIDTH 8u 682 #define S32_NVIC_IP_PRI130(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI130_SHIFT))&S32_NVIC_IP_PRI130_MASK) 683 #define S32_NVIC_IP_PRI131_MASK 0xFFu 684 #define S32_NVIC_IP_PRI131_SHIFT 0u 685 #define S32_NVIC_IP_PRI131_WIDTH 8u 686 #define S32_NVIC_IP_PRI131(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI131_SHIFT))&S32_NVIC_IP_PRI131_MASK) 687 #define S32_NVIC_IP_PRI132_MASK 0xFFu 688 #define S32_NVIC_IP_PRI132_SHIFT 0u 689 #define S32_NVIC_IP_PRI132_WIDTH 8u 690 #define S32_NVIC_IP_PRI132(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI132_SHIFT))&S32_NVIC_IP_PRI132_MASK) 691 #define S32_NVIC_IP_PRI133_MASK 0xFFu 692 #define S32_NVIC_IP_PRI133_SHIFT 0u 693 #define S32_NVIC_IP_PRI133_WIDTH 8u 694 #define S32_NVIC_IP_PRI133(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI133_SHIFT))&S32_NVIC_IP_PRI133_MASK) 695 #define S32_NVIC_IP_PRI134_MASK 0xFFu 696 #define S32_NVIC_IP_PRI134_SHIFT 0u 697 #define S32_NVIC_IP_PRI134_WIDTH 8u 698 #define S32_NVIC_IP_PRI134(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI134_SHIFT))&S32_NVIC_IP_PRI134_MASK) 699 #define S32_NVIC_IP_PRI135_MASK 0xFFu 700 #define S32_NVIC_IP_PRI135_SHIFT 0u 701 #define S32_NVIC_IP_PRI135_WIDTH 8u 702 #define S32_NVIC_IP_PRI135(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI135_SHIFT))&S32_NVIC_IP_PRI135_MASK) 703 #define S32_NVIC_IP_PRI136_MASK 0xFFu 704 #define S32_NVIC_IP_PRI136_SHIFT 0u 705 #define S32_NVIC_IP_PRI136_WIDTH 8u 706 #define S32_NVIC_IP_PRI136(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI136_SHIFT))&S32_NVIC_IP_PRI136_MASK) 707 #define S32_NVIC_IP_PRI137_MASK 0xFFu 708 #define S32_NVIC_IP_PRI137_SHIFT 0u 709 #define S32_NVIC_IP_PRI137_WIDTH 8u 710 #define S32_NVIC_IP_PRI137(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI137_SHIFT))&S32_NVIC_IP_PRI137_MASK) 711 #define S32_NVIC_IP_PRI138_MASK 0xFFu 712 #define S32_NVIC_IP_PRI138_SHIFT 0u 713 #define S32_NVIC_IP_PRI138_WIDTH 8u 714 #define S32_NVIC_IP_PRI138(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI138_SHIFT))&S32_NVIC_IP_PRI138_MASK) 715 #define S32_NVIC_IP_PRI139_MASK 0xFFu 716 #define S32_NVIC_IP_PRI139_SHIFT 0u 717 #define S32_NVIC_IP_PRI139_WIDTH 8u 718 #define S32_NVIC_IP_PRI139(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI139_SHIFT))&S32_NVIC_IP_PRI139_MASK) 719 #define S32_NVIC_IP_PRI140_MASK 0xFFu 720 #define S32_NVIC_IP_PRI140_SHIFT 0u 721 #define S32_NVIC_IP_PRI140_WIDTH 8u 722 #define S32_NVIC_IP_PRI140(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI140_SHIFT))&S32_NVIC_IP_PRI140_MASK) 723 #define S32_NVIC_IP_PRI141_MASK 0xFFu 724 #define S32_NVIC_IP_PRI141_SHIFT 0u 725 #define S32_NVIC_IP_PRI141_WIDTH 8u 726 #define S32_NVIC_IP_PRI141(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI141_SHIFT))&S32_NVIC_IP_PRI141_MASK) 727 #define S32_NVIC_IP_PRI142_MASK 0xFFu 728 #define S32_NVIC_IP_PRI142_SHIFT 0u 729 #define S32_NVIC_IP_PRI142_WIDTH 8u 730 #define S32_NVIC_IP_PRI142(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI142_SHIFT))&S32_NVIC_IP_PRI142_MASK) 731 #define S32_NVIC_IP_PRI143_MASK 0xFFu 732 #define S32_NVIC_IP_PRI143_SHIFT 0u 733 #define S32_NVIC_IP_PRI143_WIDTH 8u 734 #define S32_NVIC_IP_PRI143(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI143_SHIFT))&S32_NVIC_IP_PRI143_MASK) 735 #define S32_NVIC_IP_PRI144_MASK 0xFFu 736 #define S32_NVIC_IP_PRI144_SHIFT 0u 737 #define S32_NVIC_IP_PRI144_WIDTH 8u 738 #define S32_NVIC_IP_PRI144(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI144_SHIFT))&S32_NVIC_IP_PRI144_MASK) 739 #define S32_NVIC_IP_PRI145_MASK 0xFFu 740 #define S32_NVIC_IP_PRI145_SHIFT 0u 741 #define S32_NVIC_IP_PRI145_WIDTH 8u 742 #define S32_NVIC_IP_PRI145(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI145_SHIFT))&S32_NVIC_IP_PRI145_MASK) 743 #define S32_NVIC_IP_PRI146_MASK 0xFFu 744 #define S32_NVIC_IP_PRI146_SHIFT 0u 745 #define S32_NVIC_IP_PRI146_WIDTH 8u 746 #define S32_NVIC_IP_PRI146(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI146_SHIFT))&S32_NVIC_IP_PRI146_MASK) 747 #define S32_NVIC_IP_PRI147_MASK 0xFFu 748 #define S32_NVIC_IP_PRI147_SHIFT 0u 749 #define S32_NVIC_IP_PRI147_WIDTH 8u 750 #define S32_NVIC_IP_PRI147(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI147_SHIFT))&S32_NVIC_IP_PRI147_MASK) 751 #define S32_NVIC_IP_PRI148_MASK 0xFFu 752 #define S32_NVIC_IP_PRI148_SHIFT 0u 753 #define S32_NVIC_IP_PRI148_WIDTH 8u 754 #define S32_NVIC_IP_PRI148(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI148_SHIFT))&S32_NVIC_IP_PRI148_MASK) 755 #define S32_NVIC_IP_PRI149_MASK 0xFFu 756 #define S32_NVIC_IP_PRI149_SHIFT 0u 757 #define S32_NVIC_IP_PRI149_WIDTH 8u 758 #define S32_NVIC_IP_PRI149(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI149_SHIFT))&S32_NVIC_IP_PRI149_MASK) 759 #define S32_NVIC_IP_PRI150_MASK 0xFFu 760 #define S32_NVIC_IP_PRI150_SHIFT 0u 761 #define S32_NVIC_IP_PRI150_WIDTH 8u 762 #define S32_NVIC_IP_PRI150(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI150_SHIFT))&S32_NVIC_IP_PRI150_MASK) 763 #define S32_NVIC_IP_PRI151_MASK 0xFFu 764 #define S32_NVIC_IP_PRI151_SHIFT 0u 765 #define S32_NVIC_IP_PRI151_WIDTH 8u 766 #define S32_NVIC_IP_PRI151(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI151_SHIFT))&S32_NVIC_IP_PRI151_MASK) 767 #define S32_NVIC_IP_PRI152_MASK 0xFFu 768 #define S32_NVIC_IP_PRI152_SHIFT 0u 769 #define S32_NVIC_IP_PRI152_WIDTH 8u 770 #define S32_NVIC_IP_PRI152(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI152_SHIFT))&S32_NVIC_IP_PRI152_MASK) 771 #define S32_NVIC_IP_PRI153_MASK 0xFFu 772 #define S32_NVIC_IP_PRI153_SHIFT 0u 773 #define S32_NVIC_IP_PRI153_WIDTH 8u 774 #define S32_NVIC_IP_PRI153(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI153_SHIFT))&S32_NVIC_IP_PRI153_MASK) 775 #define S32_NVIC_IP_PRI154_MASK 0xFFu 776 #define S32_NVIC_IP_PRI154_SHIFT 0u 777 #define S32_NVIC_IP_PRI154_WIDTH 8u 778 #define S32_NVIC_IP_PRI154(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI154_SHIFT))&S32_NVIC_IP_PRI154_MASK) 779 #define S32_NVIC_IP_PRI155_MASK 0xFFu 780 #define S32_NVIC_IP_PRI155_SHIFT 0u 781 #define S32_NVIC_IP_PRI155_WIDTH 8u 782 #define S32_NVIC_IP_PRI155(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI155_SHIFT))&S32_NVIC_IP_PRI155_MASK) 783 #define S32_NVIC_IP_PRI156_MASK 0xFFu 784 #define S32_NVIC_IP_PRI156_SHIFT 0u 785 #define S32_NVIC_IP_PRI156_WIDTH 8u 786 #define S32_NVIC_IP_PRI156(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI156_SHIFT))&S32_NVIC_IP_PRI156_MASK) 787 #define S32_NVIC_IP_PRI157_MASK 0xFFu 788 #define S32_NVIC_IP_PRI157_SHIFT 0u 789 #define S32_NVIC_IP_PRI157_WIDTH 8u 790 #define S32_NVIC_IP_PRI157(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI157_SHIFT))&S32_NVIC_IP_PRI157_MASK) 791 #define S32_NVIC_IP_PRI158_MASK 0xFFu 792 #define S32_NVIC_IP_PRI158_SHIFT 0u 793 #define S32_NVIC_IP_PRI158_WIDTH 8u 794 #define S32_NVIC_IP_PRI158(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI158_SHIFT))&S32_NVIC_IP_PRI158_MASK) 795 #define S32_NVIC_IP_PRI159_MASK 0xFFu 796 #define S32_NVIC_IP_PRI159_SHIFT 0u 797 #define S32_NVIC_IP_PRI159_WIDTH 8u 798 #define S32_NVIC_IP_PRI159(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI159_SHIFT))&S32_NVIC_IP_PRI159_MASK) 799 #define S32_NVIC_IP_PRI160_MASK 0xFFu 800 #define S32_NVIC_IP_PRI160_SHIFT 0u 801 #define S32_NVIC_IP_PRI160_WIDTH 8u 802 #define S32_NVIC_IP_PRI160(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI160_SHIFT))&S32_NVIC_IP_PRI160_MASK) 803 #define S32_NVIC_IP_PRI161_MASK 0xFFu 804 #define S32_NVIC_IP_PRI161_SHIFT 0u 805 #define S32_NVIC_IP_PRI161_WIDTH 8u 806 #define S32_NVIC_IP_PRI161(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI161_SHIFT))&S32_NVIC_IP_PRI161_MASK) 807 #define S32_NVIC_IP_PRI162_MASK 0xFFu 808 #define S32_NVIC_IP_PRI162_SHIFT 0u 809 #define S32_NVIC_IP_PRI162_WIDTH 8u 810 #define S32_NVIC_IP_PRI162(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI162_SHIFT))&S32_NVIC_IP_PRI162_MASK) 811 #define S32_NVIC_IP_PRI163_MASK 0xFFu 812 #define S32_NVIC_IP_PRI163_SHIFT 0u 813 #define S32_NVIC_IP_PRI163_WIDTH 8u 814 #define S32_NVIC_IP_PRI163(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI163_SHIFT))&S32_NVIC_IP_PRI163_MASK) 815 #define S32_NVIC_IP_PRI164_MASK 0xFFu 816 #define S32_NVIC_IP_PRI164_SHIFT 0u 817 #define S32_NVIC_IP_PRI164_WIDTH 8u 818 #define S32_NVIC_IP_PRI164(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI164_SHIFT))&S32_NVIC_IP_PRI164_MASK) 819 #define S32_NVIC_IP_PRI165_MASK 0xFFu 820 #define S32_NVIC_IP_PRI165_SHIFT 0u 821 #define S32_NVIC_IP_PRI165_WIDTH 8u 822 #define S32_NVIC_IP_PRI165(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI165_SHIFT))&S32_NVIC_IP_PRI165_MASK) 823 #define S32_NVIC_IP_PRI166_MASK 0xFFu 824 #define S32_NVIC_IP_PRI166_SHIFT 0u 825 #define S32_NVIC_IP_PRI166_WIDTH 8u 826 #define S32_NVIC_IP_PRI166(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI166_SHIFT))&S32_NVIC_IP_PRI166_MASK) 827 #define S32_NVIC_IP_PRI167_MASK 0xFFu 828 #define S32_NVIC_IP_PRI167_SHIFT 0u 829 #define S32_NVIC_IP_PRI167_WIDTH 8u 830 #define S32_NVIC_IP_PRI167(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI167_SHIFT))&S32_NVIC_IP_PRI167_MASK) 831 #define S32_NVIC_IP_PRI168_MASK 0xFFu 832 #define S32_NVIC_IP_PRI168_SHIFT 0u 833 #define S32_NVIC_IP_PRI168_WIDTH 8u 834 #define S32_NVIC_IP_PRI168(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI168_SHIFT))&S32_NVIC_IP_PRI168_MASK) 835 #define S32_NVIC_IP_PRI169_MASK 0xFFu 836 #define S32_NVIC_IP_PRI169_SHIFT 0u 837 #define S32_NVIC_IP_PRI169_WIDTH 8u 838 #define S32_NVIC_IP_PRI169(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI169_SHIFT))&S32_NVIC_IP_PRI169_MASK) 839 #define S32_NVIC_IP_PRI170_MASK 0xFFu 840 #define S32_NVIC_IP_PRI170_SHIFT 0u 841 #define S32_NVIC_IP_PRI170_WIDTH 8u 842 #define S32_NVIC_IP_PRI170(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI170_SHIFT))&S32_NVIC_IP_PRI170_MASK) 843 #define S32_NVIC_IP_PRI171_MASK 0xFFu 844 #define S32_NVIC_IP_PRI171_SHIFT 0u 845 #define S32_NVIC_IP_PRI171_WIDTH 8u 846 #define S32_NVIC_IP_PRI171(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI171_SHIFT))&S32_NVIC_IP_PRI171_MASK) 847 #define S32_NVIC_IP_PRI172_MASK 0xFFu 848 #define S32_NVIC_IP_PRI172_SHIFT 0u 849 #define S32_NVIC_IP_PRI172_WIDTH 8u 850 #define S32_NVIC_IP_PRI172(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI172_SHIFT))&S32_NVIC_IP_PRI172_MASK) 851 #define S32_NVIC_IP_PRI173_MASK 0xFFu 852 #define S32_NVIC_IP_PRI173_SHIFT 0u 853 #define S32_NVIC_IP_PRI173_WIDTH 8u 854 #define S32_NVIC_IP_PRI173(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI173_SHIFT))&S32_NVIC_IP_PRI173_MASK) 855 #define S32_NVIC_IP_PRI174_MASK 0xFFu 856 #define S32_NVIC_IP_PRI174_SHIFT 0u 857 #define S32_NVIC_IP_PRI174_WIDTH 8u 858 #define S32_NVIC_IP_PRI174(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI174_SHIFT))&S32_NVIC_IP_PRI174_MASK) 859 #define S32_NVIC_IP_PRI175_MASK 0xFFu 860 #define S32_NVIC_IP_PRI175_SHIFT 0u 861 #define S32_NVIC_IP_PRI175_WIDTH 8u 862 #define S32_NVIC_IP_PRI175(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI175_SHIFT))&S32_NVIC_IP_PRI175_MASK) 863 #define S32_NVIC_IP_PRI176_MASK 0xFFu 864 #define S32_NVIC_IP_PRI176_SHIFT 0u 865 #define S32_NVIC_IP_PRI176_WIDTH 8u 866 #define S32_NVIC_IP_PRI176(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI176_SHIFT))&S32_NVIC_IP_PRI176_MASK) 867 #define S32_NVIC_IP_PRI177_MASK 0xFFu 868 #define S32_NVIC_IP_PRI177_SHIFT 0u 869 #define S32_NVIC_IP_PRI177_WIDTH 8u 870 #define S32_NVIC_IP_PRI177(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI177_SHIFT))&S32_NVIC_IP_PRI177_MASK) 871 #define S32_NVIC_IP_PRI178_MASK 0xFFu 872 #define S32_NVIC_IP_PRI178_SHIFT 0u 873 #define S32_NVIC_IP_PRI178_WIDTH 8u 874 #define S32_NVIC_IP_PRI178(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI178_SHIFT))&S32_NVIC_IP_PRI178_MASK) 875 #define S32_NVIC_IP_PRI179_MASK 0xFFu 876 #define S32_NVIC_IP_PRI179_SHIFT 0u 877 #define S32_NVIC_IP_PRI179_WIDTH 8u 878 #define S32_NVIC_IP_PRI179(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI179_SHIFT))&S32_NVIC_IP_PRI179_MASK) 879 #define S32_NVIC_IP_PRI180_MASK 0xFFu 880 #define S32_NVIC_IP_PRI180_SHIFT 0u 881 #define S32_NVIC_IP_PRI180_WIDTH 8u 882 #define S32_NVIC_IP_PRI180(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI180_SHIFT))&S32_NVIC_IP_PRI180_MASK) 883 #define S32_NVIC_IP_PRI181_MASK 0xFFu 884 #define S32_NVIC_IP_PRI181_SHIFT 0u 885 #define S32_NVIC_IP_PRI181_WIDTH 8u 886 #define S32_NVIC_IP_PRI181(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI181_SHIFT))&S32_NVIC_IP_PRI181_MASK) 887 #define S32_NVIC_IP_PRI182_MASK 0xFFu 888 #define S32_NVIC_IP_PRI182_SHIFT 0u 889 #define S32_NVIC_IP_PRI182_WIDTH 8u 890 #define S32_NVIC_IP_PRI182(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI182_SHIFT))&S32_NVIC_IP_PRI182_MASK) 891 #define S32_NVIC_IP_PRI183_MASK 0xFFu 892 #define S32_NVIC_IP_PRI183_SHIFT 0u 893 #define S32_NVIC_IP_PRI183_WIDTH 8u 894 #define S32_NVIC_IP_PRI183(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI183_SHIFT))&S32_NVIC_IP_PRI183_MASK) 895 #define S32_NVIC_IP_PRI184_MASK 0xFFu 896 #define S32_NVIC_IP_PRI184_SHIFT 0u 897 #define S32_NVIC_IP_PRI184_WIDTH 8u 898 #define S32_NVIC_IP_PRI184(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI184_SHIFT))&S32_NVIC_IP_PRI184_MASK) 899 #define S32_NVIC_IP_PRI185_MASK 0xFFu 900 #define S32_NVIC_IP_PRI185_SHIFT 0u 901 #define S32_NVIC_IP_PRI185_WIDTH 8u 902 #define S32_NVIC_IP_PRI185(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI185_SHIFT))&S32_NVIC_IP_PRI185_MASK) 903 #define S32_NVIC_IP_PRI186_MASK 0xFFu 904 #define S32_NVIC_IP_PRI186_SHIFT 0u 905 #define S32_NVIC_IP_PRI186_WIDTH 8u 906 #define S32_NVIC_IP_PRI186(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI186_SHIFT))&S32_NVIC_IP_PRI186_MASK) 907 #define S32_NVIC_IP_PRI187_MASK 0xFFu 908 #define S32_NVIC_IP_PRI187_SHIFT 0u 909 #define S32_NVIC_IP_PRI187_WIDTH 8u 910 #define S32_NVIC_IP_PRI187(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI187_SHIFT))&S32_NVIC_IP_PRI187_MASK) 911 #define S32_NVIC_IP_PRI188_MASK 0xFFu 912 #define S32_NVIC_IP_PRI188_SHIFT 0u 913 #define S32_NVIC_IP_PRI188_WIDTH 8u 914 #define S32_NVIC_IP_PRI188(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI188_SHIFT))&S32_NVIC_IP_PRI188_MASK) 915 #define S32_NVIC_IP_PRI189_MASK 0xFFu 916 #define S32_NVIC_IP_PRI189_SHIFT 0u 917 #define S32_NVIC_IP_PRI189_WIDTH 8u 918 #define S32_NVIC_IP_PRI189(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI189_SHIFT))&S32_NVIC_IP_PRI189_MASK) 919 #define S32_NVIC_IP_PRI190_MASK 0xFFu 920 #define S32_NVIC_IP_PRI190_SHIFT 0u 921 #define S32_NVIC_IP_PRI190_WIDTH 8u 922 #define S32_NVIC_IP_PRI190(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI190_SHIFT))&S32_NVIC_IP_PRI190_MASK) 923 #define S32_NVIC_IP_PRI191_MASK 0xFFu 924 #define S32_NVIC_IP_PRI191_SHIFT 0u 925 #define S32_NVIC_IP_PRI191_WIDTH 8u 926 #define S32_NVIC_IP_PRI191(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI191_SHIFT))&S32_NVIC_IP_PRI191_MASK) 927 #define S32_NVIC_IP_PRI192_MASK 0xFFu 928 #define S32_NVIC_IP_PRI192_SHIFT 0u 929 #define S32_NVIC_IP_PRI192_WIDTH 8u 930 #define S32_NVIC_IP_PRI192(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI192_SHIFT))&S32_NVIC_IP_PRI192_MASK) 931 #define S32_NVIC_IP_PRI193_MASK 0xFFu 932 #define S32_NVIC_IP_PRI193_SHIFT 0u 933 #define S32_NVIC_IP_PRI193_WIDTH 8u 934 #define S32_NVIC_IP_PRI193(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI193_SHIFT))&S32_NVIC_IP_PRI193_MASK) 935 #define S32_NVIC_IP_PRI194_MASK 0xFFu 936 #define S32_NVIC_IP_PRI194_SHIFT 0u 937 #define S32_NVIC_IP_PRI194_WIDTH 8u 938 #define S32_NVIC_IP_PRI194(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI194_SHIFT))&S32_NVIC_IP_PRI194_MASK) 939 #define S32_NVIC_IP_PRI195_MASK 0xFFu 940 #define S32_NVIC_IP_PRI195_SHIFT 0u 941 #define S32_NVIC_IP_PRI195_WIDTH 8u 942 #define S32_NVIC_IP_PRI195(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI195_SHIFT))&S32_NVIC_IP_PRI195_MASK) 943 #define S32_NVIC_IP_PRI196_MASK 0xFFu 944 #define S32_NVIC_IP_PRI196_SHIFT 0u 945 #define S32_NVIC_IP_PRI196_WIDTH 8u 946 #define S32_NVIC_IP_PRI196(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI196_SHIFT))&S32_NVIC_IP_PRI196_MASK) 947 #define S32_NVIC_IP_PRI197_MASK 0xFFu 948 #define S32_NVIC_IP_PRI197_SHIFT 0u 949 #define S32_NVIC_IP_PRI197_WIDTH 8u 950 #define S32_NVIC_IP_PRI197(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI197_SHIFT))&S32_NVIC_IP_PRI197_MASK) 951 #define S32_NVIC_IP_PRI198_MASK 0xFFu 952 #define S32_NVIC_IP_PRI198_SHIFT 0u 953 #define S32_NVIC_IP_PRI198_WIDTH 8u 954 #define S32_NVIC_IP_PRI198(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI198_SHIFT))&S32_NVIC_IP_PRI198_MASK) 955 #define S32_NVIC_IP_PRI199_MASK 0xFFu 956 #define S32_NVIC_IP_PRI199_SHIFT 0u 957 #define S32_NVIC_IP_PRI199_WIDTH 8u 958 #define S32_NVIC_IP_PRI199(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI199_SHIFT))&S32_NVIC_IP_PRI199_MASK) 959 #define S32_NVIC_IP_PRI200_MASK 0xFFu 960 #define S32_NVIC_IP_PRI200_SHIFT 0u 961 #define S32_NVIC_IP_PRI200_WIDTH 8u 962 #define S32_NVIC_IP_PRI200(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI200_SHIFT))&S32_NVIC_IP_PRI200_MASK) 963 #define S32_NVIC_IP_PRI201_MASK 0xFFu 964 #define S32_NVIC_IP_PRI201_SHIFT 0u 965 #define S32_NVIC_IP_PRI201_WIDTH 8u 966 #define S32_NVIC_IP_PRI201(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI201_SHIFT))&S32_NVIC_IP_PRI201_MASK) 967 #define S32_NVIC_IP_PRI202_MASK 0xFFu 968 #define S32_NVIC_IP_PRI202_SHIFT 0u 969 #define S32_NVIC_IP_PRI202_WIDTH 8u 970 #define S32_NVIC_IP_PRI202(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI202_SHIFT))&S32_NVIC_IP_PRI202_MASK) 971 #define S32_NVIC_IP_PRI203_MASK 0xFFu 972 #define S32_NVIC_IP_PRI203_SHIFT 0u 973 #define S32_NVIC_IP_PRI203_WIDTH 8u 974 #define S32_NVIC_IP_PRI203(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI203_SHIFT))&S32_NVIC_IP_PRI203_MASK) 975 #define S32_NVIC_IP_PRI204_MASK 0xFFu 976 #define S32_NVIC_IP_PRI204_SHIFT 0u 977 #define S32_NVIC_IP_PRI204_WIDTH 8u 978 #define S32_NVIC_IP_PRI204(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI204_SHIFT))&S32_NVIC_IP_PRI204_MASK) 979 #define S32_NVIC_IP_PRI205_MASK 0xFFu 980 #define S32_NVIC_IP_PRI205_SHIFT 0u 981 #define S32_NVIC_IP_PRI205_WIDTH 8u 982 #define S32_NVIC_IP_PRI205(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI205_SHIFT))&S32_NVIC_IP_PRI205_MASK) 983 #define S32_NVIC_IP_PRI206_MASK 0xFFu 984 #define S32_NVIC_IP_PRI206_SHIFT 0u 985 #define S32_NVIC_IP_PRI206_WIDTH 8u 986 #define S32_NVIC_IP_PRI206(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI206_SHIFT))&S32_NVIC_IP_PRI206_MASK) 987 #define S32_NVIC_IP_PRI207_MASK 0xFFu 988 #define S32_NVIC_IP_PRI207_SHIFT 0u 989 #define S32_NVIC_IP_PRI207_WIDTH 8u 990 #define S32_NVIC_IP_PRI207(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI207_SHIFT))&S32_NVIC_IP_PRI207_MASK) 991 #define S32_NVIC_IP_PRI208_MASK 0xFFu 992 #define S32_NVIC_IP_PRI208_SHIFT 0u 993 #define S32_NVIC_IP_PRI208_WIDTH 8u 994 #define S32_NVIC_IP_PRI208(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI208_SHIFT))&S32_NVIC_IP_PRI208_MASK) 995 #define S32_NVIC_IP_PRI209_MASK 0xFFu 996 #define S32_NVIC_IP_PRI209_SHIFT 0u 997 #define S32_NVIC_IP_PRI209_WIDTH 8u 998 #define S32_NVIC_IP_PRI209(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI209_SHIFT))&S32_NVIC_IP_PRI209_MASK) 999 #define S32_NVIC_IP_PRI210_MASK 0xFFu 1000 #define S32_NVIC_IP_PRI210_SHIFT 0u 1001 #define S32_NVIC_IP_PRI210_WIDTH 8u 1002 #define S32_NVIC_IP_PRI210(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI210_SHIFT))&S32_NVIC_IP_PRI210_MASK) 1003 #define S32_NVIC_IP_PRI211_MASK 0xFFu 1004 #define S32_NVIC_IP_PRI211_SHIFT 0u 1005 #define S32_NVIC_IP_PRI211_WIDTH 8u 1006 #define S32_NVIC_IP_PRI211(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI211_SHIFT))&S32_NVIC_IP_PRI211_MASK) 1007 #define S32_NVIC_IP_PRI212_MASK 0xFFu 1008 #define S32_NVIC_IP_PRI212_SHIFT 0u 1009 #define S32_NVIC_IP_PRI212_WIDTH 8u 1010 #define S32_NVIC_IP_PRI212(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI212_SHIFT))&S32_NVIC_IP_PRI212_MASK) 1011 #define S32_NVIC_IP_PRI213_MASK 0xFFu 1012 #define S32_NVIC_IP_PRI213_SHIFT 0u 1013 #define S32_NVIC_IP_PRI213_WIDTH 8u 1014 #define S32_NVIC_IP_PRI213(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI213_SHIFT))&S32_NVIC_IP_PRI213_MASK) 1015 #define S32_NVIC_IP_PRI214_MASK 0xFFu 1016 #define S32_NVIC_IP_PRI214_SHIFT 0u 1017 #define S32_NVIC_IP_PRI214_WIDTH 8u 1018 #define S32_NVIC_IP_PRI214(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI214_SHIFT))&S32_NVIC_IP_PRI214_MASK) 1019 #define S32_NVIC_IP_PRI215_MASK 0xFFu 1020 #define S32_NVIC_IP_PRI215_SHIFT 0u 1021 #define S32_NVIC_IP_PRI215_WIDTH 8u 1022 #define S32_NVIC_IP_PRI215(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI215_SHIFT))&S32_NVIC_IP_PRI215_MASK) 1023 #define S32_NVIC_IP_PRI216_MASK 0xFFu 1024 #define S32_NVIC_IP_PRI216_SHIFT 0u 1025 #define S32_NVIC_IP_PRI216_WIDTH 8u 1026 #define S32_NVIC_IP_PRI216(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI216_SHIFT))&S32_NVIC_IP_PRI216_MASK) 1027 #define S32_NVIC_IP_PRI217_MASK 0xFFu 1028 #define S32_NVIC_IP_PRI217_SHIFT 0u 1029 #define S32_NVIC_IP_PRI217_WIDTH 8u 1030 #define S32_NVIC_IP_PRI217(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI217_SHIFT))&S32_NVIC_IP_PRI217_MASK) 1031 #define S32_NVIC_IP_PRI218_MASK 0xFFu 1032 #define S32_NVIC_IP_PRI218_SHIFT 0u 1033 #define S32_NVIC_IP_PRI218_WIDTH 8u 1034 #define S32_NVIC_IP_PRI218(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI218_SHIFT))&S32_NVIC_IP_PRI218_MASK) 1035 #define S32_NVIC_IP_PRI219_MASK 0xFFu 1036 #define S32_NVIC_IP_PRI219_SHIFT 0u 1037 #define S32_NVIC_IP_PRI219_WIDTH 8u 1038 #define S32_NVIC_IP_PRI219(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI219_SHIFT))&S32_NVIC_IP_PRI219_MASK) 1039 #define S32_NVIC_IP_PRI220_MASK 0xFFu 1040 #define S32_NVIC_IP_PRI220_SHIFT 0u 1041 #define S32_NVIC_IP_PRI220_WIDTH 8u 1042 #define S32_NVIC_IP_PRI220(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI220_SHIFT))&S32_NVIC_IP_PRI220_MASK) 1043 #define S32_NVIC_IP_PRI221_MASK 0xFFu 1044 #define S32_NVIC_IP_PRI221_SHIFT 0u 1045 #define S32_NVIC_IP_PRI221_WIDTH 8u 1046 #define S32_NVIC_IP_PRI221(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI221_SHIFT))&S32_NVIC_IP_PRI221_MASK) 1047 #define S32_NVIC_IP_PRI222_MASK 0xFFu 1048 #define S32_NVIC_IP_PRI222_SHIFT 0u 1049 #define S32_NVIC_IP_PRI222_WIDTH 8u 1050 #define S32_NVIC_IP_PRI222(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI222_SHIFT))&S32_NVIC_IP_PRI222_MASK) 1051 #define S32_NVIC_IP_PRI223_MASK 0xFFu 1052 #define S32_NVIC_IP_PRI223_SHIFT 0u 1053 #define S32_NVIC_IP_PRI223_WIDTH 8u 1054 #define S32_NVIC_IP_PRI223(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI223_SHIFT))&S32_NVIC_IP_PRI223_MASK) 1055 #define S32_NVIC_IP_PRI224_MASK 0xFFu 1056 #define S32_NVIC_IP_PRI224_SHIFT 0u 1057 #define S32_NVIC_IP_PRI224_WIDTH 8u 1058 #define S32_NVIC_IP_PRI224(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI224_SHIFT))&S32_NVIC_IP_PRI224_MASK) 1059 #define S32_NVIC_IP_PRI225_MASK 0xFFu 1060 #define S32_NVIC_IP_PRI225_SHIFT 0u 1061 #define S32_NVIC_IP_PRI225_WIDTH 8u 1062 #define S32_NVIC_IP_PRI225(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI225_SHIFT))&S32_NVIC_IP_PRI225_MASK) 1063 #define S32_NVIC_IP_PRI226_MASK 0xFFu 1064 #define S32_NVIC_IP_PRI226_SHIFT 0u 1065 #define S32_NVIC_IP_PRI226_WIDTH 8u 1066 #define S32_NVIC_IP_PRI226(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI226_SHIFT))&S32_NVIC_IP_PRI226_MASK) 1067 #define S32_NVIC_IP_PRI227_MASK 0xFFu 1068 #define S32_NVIC_IP_PRI227_SHIFT 0u 1069 #define S32_NVIC_IP_PRI227_WIDTH 8u 1070 #define S32_NVIC_IP_PRI227(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI227_SHIFT))&S32_NVIC_IP_PRI227_MASK) 1071 #define S32_NVIC_IP_PRI228_MASK 0xFFu 1072 #define S32_NVIC_IP_PRI228_SHIFT 0u 1073 #define S32_NVIC_IP_PRI228_WIDTH 8u 1074 #define S32_NVIC_IP_PRI228(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI228_SHIFT))&S32_NVIC_IP_PRI228_MASK) 1075 #define S32_NVIC_IP_PRI229_MASK 0xFFu 1076 #define S32_NVIC_IP_PRI229_SHIFT 0u 1077 #define S32_NVIC_IP_PRI229_WIDTH 8u 1078 #define S32_NVIC_IP_PRI229(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI229_SHIFT))&S32_NVIC_IP_PRI229_MASK) 1079 #define S32_NVIC_IP_PRI230_MASK 0xFFu 1080 #define S32_NVIC_IP_PRI230_SHIFT 0u 1081 #define S32_NVIC_IP_PRI230_WIDTH 8u 1082 #define S32_NVIC_IP_PRI230(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI230_SHIFT))&S32_NVIC_IP_PRI230_MASK) 1083 #define S32_NVIC_IP_PRI231_MASK 0xFFu 1084 #define S32_NVIC_IP_PRI231_SHIFT 0u 1085 #define S32_NVIC_IP_PRI231_WIDTH 8u 1086 #define S32_NVIC_IP_PRI231(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI231_SHIFT))&S32_NVIC_IP_PRI231_MASK) 1087 #define S32_NVIC_IP_PRI232_MASK 0xFFu 1088 #define S32_NVIC_IP_PRI232_SHIFT 0u 1089 #define S32_NVIC_IP_PRI232_WIDTH 8u 1090 #define S32_NVIC_IP_PRI232(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI232_SHIFT))&S32_NVIC_IP_PRI232_MASK) 1091 #define S32_NVIC_IP_PRI233_MASK 0xFFu 1092 #define S32_NVIC_IP_PRI233_SHIFT 0u 1093 #define S32_NVIC_IP_PRI233_WIDTH 8u 1094 #define S32_NVIC_IP_PRI233(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI233_SHIFT))&S32_NVIC_IP_PRI233_MASK) 1095 #define S32_NVIC_IP_PRI234_MASK 0xFFu 1096 #define S32_NVIC_IP_PRI234_SHIFT 0u 1097 #define S32_NVIC_IP_PRI234_WIDTH 8u 1098 #define S32_NVIC_IP_PRI234(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI234_SHIFT))&S32_NVIC_IP_PRI234_MASK) 1099 #define S32_NVIC_IP_PRI235_MASK 0xFFu 1100 #define S32_NVIC_IP_PRI235_SHIFT 0u 1101 #define S32_NVIC_IP_PRI235_WIDTH 8u 1102 #define S32_NVIC_IP_PRI235(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI235_SHIFT))&S32_NVIC_IP_PRI235_MASK) 1103 #define S32_NVIC_IP_PRI236_MASK 0xFFu 1104 #define S32_NVIC_IP_PRI236_SHIFT 0u 1105 #define S32_NVIC_IP_PRI236_WIDTH 8u 1106 #define S32_NVIC_IP_PRI236(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI236_SHIFT))&S32_NVIC_IP_PRI236_MASK) 1107 #define S32_NVIC_IP_PRI237_MASK 0xFFu 1108 #define S32_NVIC_IP_PRI237_SHIFT 0u 1109 #define S32_NVIC_IP_PRI237_WIDTH 8u 1110 #define S32_NVIC_IP_PRI237(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI237_SHIFT))&S32_NVIC_IP_PRI237_MASK) 1111 #define S32_NVIC_IP_PRI238_MASK 0xFFu 1112 #define S32_NVIC_IP_PRI238_SHIFT 0u 1113 #define S32_NVIC_IP_PRI238_WIDTH 8u 1114 #define S32_NVIC_IP_PRI238(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI238_SHIFT))&S32_NVIC_IP_PRI238_MASK) 1115 #define S32_NVIC_IP_PRI239_MASK 0xFFu 1116 #define S32_NVIC_IP_PRI239_SHIFT 0u 1117 #define S32_NVIC_IP_PRI239_WIDTH 8u 1118 #define S32_NVIC_IP_PRI239(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI239_SHIFT))&S32_NVIC_IP_PRI239_MASK) 1119 #define S32_NVIC_IP_PRI240_MASK 0xFFu 1120 #define S32_NVIC_IP_PRI240_SHIFT 0u 1121 #define S32_NVIC_IP_PRI240_WIDTH 8u 1122 #define S32_NVIC_IP_PRI240(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI240_SHIFT))&S32_NVIC_IP_PRI240_MASK) 1123 #define S32_NVIC_IP_PRI241_MASK 0xFFu 1124 #define S32_NVIC_IP_PRI241_SHIFT 0u 1125 #define S32_NVIC_IP_PRI241_WIDTH 8u 1126 #define S32_NVIC_IP_PRI241(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI241_SHIFT))&S32_NVIC_IP_PRI241_MASK) 1127 #define S32_NVIC_IP_PRI241_MASK 0xFFu 1128 #define S32_NVIC_IP_PRI242_SHIFT 0u 1129 #define S32_NVIC_IP_PRI242_WIDTH 8u 1130 #define S32_NVIC_IP_PRI242(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI242_SHIFT))&S32_NVIC_IP_PRI242_MASK) 1131 #define S32_NVIC_IP_PRI242_MASK 0xFFu 1132 #define S32_NVIC_IP_PRI242_SHIFT 0u 1133 #define S32_NVIC_IP_PRI243_WIDTH 8u 1134 #define S32_NVIC_IP_PRI243(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI243_SHIFT))&S32_NVIC_IP_PRI243_MASK) 1135 #define S32_NVIC_IP_PRI243_MASK 0xFFu 1136 #define S32_NVIC_IP_PRI243_SHIFT 0u 1137 #define S32_NVIC_IP_PRI243_WIDTH 8u 1138 #define S32_NVIC_IP_PRI244(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI244_SHIFT))&S32_NVIC_IP_PRI244_MASK) 1139 #define S32_NVIC_IP_PRI244_MASK 0xFFu 1140 #define S32_NVIC_IP_PRI244_SHIFT 0u 1141 #define S32_NVIC_IP_PRI244_WIDTH 8u 1142 #define S32_NVIC_IP_PRI244(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI244_SHIFT))&S32_NVIC_IP_PRI244_MASK) 1143 #define S32_NVIC_IP_PRI245_MASK 0xFFu 1144 #define S32_NVIC_IP_PRI245_SHIFT 0u 1145 #define S32_NVIC_IP_PRI245_WIDTH 8u 1146 #define S32_NVIC_IP_PRI245(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI245_SHIFT))&S32_NVIC_IP_PRI245_MASK) 1147 #define S32_NVIC_IP_PRI245_MASK 0xFFu 1148 #define S32_NVIC_IP_PRI246_SHIFT 0u 1149 #define S32_NVIC_IP_PRI246_WIDTH 8u 1150 #define S32_NVIC_IP_PRI246(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI246_SHIFT))&S32_NVIC_IP_PRI246_MASK) 1151 #define S32_NVIC_IP_PRI246_MASK 0xFFu 1152 #define S32_NVIC_IP_PRI246_SHIFT 0u 1153 #define S32_NVIC_IP_PRI247_WIDTH 8u 1154 #define S32_NVIC_IP_PRI247(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI247_SHIFT))&S32_NVIC_IP_PRI247_MASK) 1155 #define S32_NVIC_IP_PRI247_MASK 0xFFu 1156 #define S32_NVIC_IP_PRI247_SHIFT 0u 1157 #define S32_NVIC_IP_PRI247_WIDTH 8u 1158 #define S32_NVIC_IP_PRI248(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI248_SHIFT))&S32_NVIC_IP_PRI248_MASK) 1159 #define S32_NVIC_IP_PRI248_MASK 0xFFu 1160 #define S32_NVIC_IP_PRI248_SHIFT 0u 1161 #define S32_NVIC_IP_PRI248_WIDTH 8u 1162 #define S32_NVIC_IP_PRI248(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI248_SHIFT))&S32_NVIC_IP_PRI248_MASK) 1163 #define S32_NVIC_IP_PRI249_MASK 0xFFu 1164 #define S32_NVIC_IP_PRI249_SHIFT 0u 1165 #define S32_NVIC_IP_PRI249_WIDTH 8u 1166 #define S32_NVIC_IP_PRI249(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI249_SHIFT))&S32_NVIC_IP_PRI249_MASK) 1167 #define S32_NVIC_IP_PRI249_MASK 0xFFu 1168 #define S32_NVIC_IP_PRI250_SHIFT 0u 1169 #define S32_NVIC_IP_PRI250_WIDTH 8u 1170 #define S32_NVIC_IP_PRI250(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI250_SHIFT))&S32_NVIC_IP_PRI250_MASK) 1171 #define S32_NVIC_IP_PRI250_MASK 0xFFu 1172 #define S32_NVIC_IP_PRI250_SHIFT 0u 1173 #define S32_NVIC_IP_PRI251_WIDTH 8u 1174 #define S32_NVIC_IP_PRI251(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI251_SHIFT))&S32_NVIC_IP_PRI251_MASK) 1175 #define S32_NVIC_IP_PRI251_MASK 0xFFu 1176 #define S32_NVIC_IP_PRI251_SHIFT 0u 1177 #define S32_NVIC_IP_PRI251_WIDTH 8u 1178 #define S32_NVIC_IP_PRI252(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI252_SHIFT))&S32_NVIC_IP_PRI252_MASK) 1179 #define S32_NVIC_IP_PRI252_MASK 0xFFu 1180 #define S32_NVIC_IP_PRI252_SHIFT 0u 1181 #define S32_NVIC_IP_PRI252_WIDTH 8u 1182 #define S32_NVIC_IP_PRI252(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI252_SHIFT))&S32_NVIC_IP_PRI252_MASK) 1183 #define S32_NVIC_IP_PRI253_MASK 0xFFu 1184 #define S32_NVIC_IP_PRI253_SHIFT 0u 1185 #define S32_NVIC_IP_PRI253_WIDTH 8u 1186 #define S32_NVIC_IP_PRI253(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI253_SHIFT))&S32_NVIC_IP_PRI253_MASK) 1187 #define S32_NVIC_IP_PRI253_MASK 0xFFu 1188 #define S32_NVIC_IP_PRI254_SHIFT 0u 1189 #define S32_NVIC_IP_PRI254_WIDTH 8u 1190 #define S32_NVIC_IP_PRI254(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI254_SHIFT))&S32_NVIC_IP_PRI254_MASK) 1191 #define S32_NVIC_IP_PRI254_MASK 0xFFu 1192 #define S32_NVIC_IP_PRI254_SHIFT 0u 1193 #define S32_NVIC_IP_PRI255_WIDTH 8u 1194 #define S32_NVIC_IP_PRI255(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI255_SHIFT))&S32_NVIC_IP_PRI255_MASK) 1195 #define S32_NVIC_IP_PRI255_MASK 0xFFu 1196 #define S32_NVIC_IP_PRI255_SHIFT 0u 1197 #define S32_NVIC_IP_PRI255_WIDTH 8u 1198 #define S32_NVIC_IP_PRI256(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI256_SHIFT))&S32_NVIC_IP_PRI256_MASK) 1199 #define S32_NVIC_IP_PRI256_MASK 0xFFu 1200 #define S32_NVIC_IP_PRI256_SHIFT 0u 1201 #define S32_NVIC_IP_PRI256_WIDTH 8u 1202 #define S32_NVIC_IP_PRI256(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI256_SHIFT))&S32_NVIC_IP_PRI256_MASK) 1203 #define S32_NVIC_IP_PRI257_MASK 0xFFu 1204 #define S32_NVIC_IP_PRI257_SHIFT 0u 1205 #define S32_NVIC_IP_PRI257_WIDTH 8u 1206 #define S32_NVIC_IP_PRI257(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI257_SHIFT))&S32_NVIC_IP_PRI257_MASK) 1207 #define S32_NVIC_IP_PRI257_MASK 0xFFu 1208 #define S32_NVIC_IP_PRI258_SHIFT 0u 1209 #define S32_NVIC_IP_PRI258_WIDTH 8u 1210 #define S32_NVIC_IP_PRI258(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI258_SHIFT))&S32_NVIC_IP_PRI258_MASK) 1211 #define S32_NVIC_IP_PRI258_MASK 0xFFu 1212 #define S32_NVIC_IP_PRI258_SHIFT 0u 1213 #define S32_NVIC_IP_PRI259_WIDTH 8u 1214 #define S32_NVIC_IP_PRI259(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI259_SHIFT))&S32_NVIC_IP_PRI259_MASK) 1215 #define S32_NVIC_IP_PRI259_MASK 0xFFu 1216 #define S32_NVIC_IP_PRI259_SHIFT 0u 1217 #define S32_NVIC_IP_PRI259_WIDTH 8u 1218 #define S32_NVIC_IP_PRI260(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI260_SHIFT))&S32_NVIC_IP_PRI260_MASK) 1219 #define S32_NVIC_IP_PRI260_MASK 0xFFu 1220 #define S32_NVIC_IP_PRI260_SHIFT 0u 1221 #define S32_NVIC_IP_PRI260_WIDTH 8u 1222 #define S32_NVIC_IP_PRI260(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI260_SHIFT))&S32_NVIC_IP_PRI260_MASK) 1223 #define S32_NVIC_IP_PRI261_MASK 0xFFu 1224 #define S32_NVIC_IP_PRI261_SHIFT 0u 1225 #define S32_NVIC_IP_PRI261_WIDTH 8u 1226 #define S32_NVIC_IP_PRI261(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI261_SHIFT))&S32_NVIC_IP_PRI261_MASK) 1227 #define S32_NVIC_IP_PRI261_MASK 0xFFu 1228 #define S32_NVIC_IP_PRI262_SHIFT 0u 1229 #define S32_NVIC_IP_PRI262_WIDTH 8u 1230 #define S32_NVIC_IP_PRI262(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI262_SHIFT))&S32_NVIC_IP_PRI262_MASK) 1231 #define S32_NVIC_IP_PRI262_MASK 0xFFu 1232 #define S32_NVIC_IP_PRI262_SHIFT 0u 1233 #define S32_NVIC_IP_PRI263_WIDTH 8u 1234 #define S32_NVIC_IP_PRI263(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI263_SHIFT))&S32_NVIC_IP_PRI263_MASK) 1235 #define S32_NVIC_IP_PRI263_MASK 0xFFu 1236 #define S32_NVIC_IP_PRI263_SHIFT 0u 1237 #define S32_NVIC_IP_PRI263_WIDTH 8u 1238 #define S32_NVIC_IP_PRI264(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI264_SHIFT))&S32_NVIC_IP_PRI264_MASK) 1239 #define S32_NVIC_IP_PRI264_MASK 0xFFu 1240 #define S32_NVIC_IP_PRI264_SHIFT 0u 1241 #define S32_NVIC_IP_PRI264_WIDTH 8u 1242 #define S32_NVIC_IP_PRI264(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI264_SHIFT))&S32_NVIC_IP_PRI264_MASK) 1243 #define S32_NVIC_IP_PRI265_MASK 0xFFu 1244 #define S32_NVIC_IP_PRI265_SHIFT 0u 1245 #define S32_NVIC_IP_PRI265_WIDTH 8u 1246 #define S32_NVIC_IP_PRI265(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI265_SHIFT))&S32_NVIC_IP_PRI265_MASK) 1247 #define S32_NVIC_IP_PRI265_MASK 0xFFu 1248 #define S32_NVIC_IP_PRI266_SHIFT 0u 1249 #define S32_NVIC_IP_PRI266_WIDTH 8u 1250 #define S32_NVIC_IP_PRI266(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI266_SHIFT))&S32_NVIC_IP_PRI266_MASK) 1251 #define S32_NVIC_IP_PRI266_MASK 0xFFu 1252 #define S32_NVIC_IP_PRI266_SHIFT 0u 1253 #define S32_NVIC_IP_PRI267_WIDTH 8u 1254 #define S32_NVIC_IP_PRI267(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI267_SHIFT))&S32_NVIC_IP_PRI267_MASK) 1255 #define S32_NVIC_IP_PRI267_MASK 0xFFu 1256 #define S32_NVIC_IP_PRI267_SHIFT 0u 1257 #define S32_NVIC_IP_PRI267_WIDTH 8u 1258 #define S32_NVIC_IP_PRI268(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI268_SHIFT))&S32_NVIC_IP_PRI268_MASK) 1259 #define S32_NVIC_IP_PRI268_MASK 0xFFu 1260 #define S32_NVIC_IP_PRI268_SHIFT 0u 1261 #define S32_NVIC_IP_PRI268_WIDTH 8u 1262 #define S32_NVIC_IP_PRI268(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI268_SHIFT))&S32_NVIC_IP_PRI268_MASK) 1263 #define S32_NVIC_IP_PRI269_MASK 0xFFu 1264 #define S32_NVIC_IP_PRI269_SHIFT 0u 1265 #define S32_NVIC_IP_PRI269_WIDTH 8u 1266 #define S32_NVIC_IP_PRI269(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI269_SHIFT))&S32_NVIC_IP_PRI269_MASK) 1267 #define S32_NVIC_IP_PRI269_MASK 0xFFu 1268 #define S32_NVIC_IP_PRI270_SHIFT 0u 1269 #define S32_NVIC_IP_PRI270_WIDTH 8u 1270 #define S32_NVIC_IP_PRI270(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI270_SHIFT))&S32_NVIC_IP_PRI270_MASK) 1271 #define S32_NVIC_IP_PRI270_MASK 0xFFu 1272 #define S32_NVIC_IP_PRI270_SHIFT 0u 1273 #define S32_NVIC_IP_PRI271_WIDTH 8u 1274 #define S32_NVIC_IP_PRI271(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI271_SHIFT))&S32_NVIC_IP_PRI271_MASK) 1275 #define S32_NVIC_IP_PRI271_MASK 0xFFu 1276 #define S32_NVIC_IP_PRI271_SHIFT 0u 1277 #define S32_NVIC_IP_PRI271_WIDTH 8u 1278 #define S32_NVIC_IP_PRI272(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI272_SHIFT))&S32_NVIC_IP_PRI272_MASK) 1279 #define S32_NVIC_IP_PRI272_MASK 0xFFu 1280 #define S32_NVIC_IP_PRI272_SHIFT 0u 1281 #define S32_NVIC_IP_PRI272_WIDTH 8u 1282 #define S32_NVIC_IP_PRI272(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI272_SHIFT))&S32_NVIC_IP_PRI272_MASK) 1283 #define S32_NVIC_IP_PRI273_MASK 0xFFu 1284 #define S32_NVIC_IP_PRI273_SHIFT 0u 1285 #define S32_NVIC_IP_PRI273_WIDTH 8u 1286 #define S32_NVIC_IP_PRI273(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI273_SHIFT))&S32_NVIC_IP_PRI273_MASK) 1287 #define S32_NVIC_IP_PRI273_MASK 0xFFu 1288 #define S32_NVIC_IP_PRI274_SHIFT 0u 1289 #define S32_NVIC_IP_PRI274_WIDTH 8u 1290 #define S32_NVIC_IP_PRI274(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI274_SHIFT))&S32_NVIC_IP_PRI274_MASK) 1291 #define S32_NVIC_IP_PRI274_MASK 0xFFu 1292 #define S32_NVIC_IP_PRI274_SHIFT 0u 1293 #define S32_NVIC_IP_PRI275_WIDTH 8u 1294 #define S32_NVIC_IP_PRI275(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI275_SHIFT))&S32_NVIC_IP_PRI275_MASK) 1295 #define S32_NVIC_IP_PRI275_MASK 0xFFu 1296 #define S32_NVIC_IP_PRI275_SHIFT 0u 1297 #define S32_NVIC_IP_PRI275_WIDTH 8u 1298 #define S32_NVIC_IP_PRI276(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI276_SHIFT))&S32_NVIC_IP_PRI276_MASK) 1299 #define S32_NVIC_IP_PRI276_MASK 0xFFu 1300 #define S32_NVIC_IP_PRI276_SHIFT 0u 1301 #define S32_NVIC_IP_PRI276_WIDTH 8u 1302 #define S32_NVIC_IP_PRI276(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI276_SHIFT))&S32_NVIC_IP_PRI276_MASK) 1303 #define S32_NVIC_IP_PRI277_MASK 0xFFu 1304 #define S32_NVIC_IP_PRI277_SHIFT 0u 1305 #define S32_NVIC_IP_PRI277_WIDTH 8u 1306 #define S32_NVIC_IP_PRI277(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI277_SHIFT))&S32_NVIC_IP_PRI277_MASK) 1307 #define S32_NVIC_IP_PRI277_MASK 0xFFu 1308 #define S32_NVIC_IP_PRI278_SHIFT 0u 1309 #define S32_NVIC_IP_PRI278_WIDTH 8u 1310 #define S32_NVIC_IP_PRI278(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI278_SHIFT))&S32_NVIC_IP_PRI278_MASK) 1311 #define S32_NVIC_IP_PRI278_MASK 0xFFu 1312 #define S32_NVIC_IP_PRI278_SHIFT 0u 1313 #define S32_NVIC_IP_PRI279_WIDTH 8u 1314 #define S32_NVIC_IP_PRI279(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI279_SHIFT))&S32_NVIC_IP_PRI279_MASK) 1315 #define S32_NVIC_IP_PRI279_MASK 0xFFu 1316 #define S32_NVIC_IP_PRI279_SHIFT 0u 1317 #define S32_NVIC_IP_PRI279_WIDTH 8u 1318 #define S32_NVIC_IP_PRI280(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI280_SHIFT))&S32_NVIC_IP_PRI280_MASK) 1319 #define S32_NVIC_IP_PRI280_MASK 0xFFu 1320 #define S32_NVIC_IP_PRI280_SHIFT 0u 1321 #define S32_NVIC_IP_PRI280_WIDTH 8u 1322 #define S32_NVIC_IP_PRI280(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI280_SHIFT))&S32_NVIC_IP_PRI280_MASK) 1323 #define S32_NVIC_IP_PRI281_MASK 0xFFu 1324 #define S32_NVIC_IP_PRI281_SHIFT 0u 1325 #define S32_NVIC_IP_PRI281_WIDTH 8u 1326 #define S32_NVIC_IP_PRI281(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI281_SHIFT))&S32_NVIC_IP_PRI281_MASK) 1327 #define S32_NVIC_IP_PRI281_MASK 0xFFu 1328 #define S32_NVIC_IP_PRI282_SHIFT 0u 1329 #define S32_NVIC_IP_PRI282_WIDTH 8u 1330 #define S32_NVIC_IP_PRI282(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI282_SHIFT))&S32_NVIC_IP_PRI282_MASK) 1331 #define S32_NVIC_IP_PRI282_MASK 0xFFu 1332 #define S32_NVIC_IP_PRI282_SHIFT 0u 1333 #define S32_NVIC_IP_PRI283_WIDTH 8u 1334 #define S32_NVIC_IP_PRI283(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI283_SHIFT))&S32_NVIC_IP_PRI283_MASK) 1335 #define S32_NVIC_IP_PRI283_MASK 0xFFu 1336 #define S32_NVIC_IP_PRI283_SHIFT 0u 1337 #define S32_NVIC_IP_PRI283_WIDTH 8u 1338 #define S32_NVIC_IP_PRI284(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI284_SHIFT))&S32_NVIC_IP_PRI284_MASK) 1339 #define S32_NVIC_IP_PRI284_MASK 0xFFu 1340 #define S32_NVIC_IP_PRI284_SHIFT 0u 1341 #define S32_NVIC_IP_PRI284_WIDTH 8u 1342 #define S32_NVIC_IP_PRI284(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI284_SHIFT))&S32_NVIC_IP_PRI284_MASK) 1343 #define S32_NVIC_IP_PRI285_MASK 0xFFu 1344 #define S32_NVIC_IP_PRI285_SHIFT 0u 1345 #define S32_NVIC_IP_PRI285_WIDTH 8u 1346 #define S32_NVIC_IP_PRI285(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI285_SHIFT))&S32_NVIC_IP_PRI285_MASK) 1347 #define S32_NVIC_IP_PRI285_MASK 0xFFu 1348 #define S32_NVIC_IP_PRI286_SHIFT 0u 1349 #define S32_NVIC_IP_PRI286_WIDTH 8u 1350 #define S32_NVIC_IP_PRI286(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI286_SHIFT))&S32_NVIC_IP_PRI286_MASK) 1351 #define S32_NVIC_IP_PRI286_MASK 0xFFu 1352 #define S32_NVIC_IP_PRI286_SHIFT 0u 1353 #define S32_NVIC_IP_PRI287_WIDTH 8u 1354 #define S32_NVIC_IP_PRI287(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI287_SHIFT))&S32_NVIC_IP_PRI287_MASK) 1355 #define S32_NVIC_IP_PRI287_MASK 0xFFu 1356 #define S32_NVIC_IP_PRI287_SHIFT 0u 1357 #define S32_NVIC_IP_PRI287_WIDTH 8u 1358 #define S32_NVIC_IP_PRI288(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI288_SHIFT))&S32_NVIC_IP_PRI288_MASK) 1359 #define S32_NVIC_IP_PRI288_MASK 0xFFu 1360 #define S32_NVIC_IP_PRI288_SHIFT 0u 1361 #define S32_NVIC_IP_PRI288_WIDTH 8u 1362 #define S32_NVIC_IP_PRI288(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI288_SHIFT))&S32_NVIC_IP_PRI288_MASK) 1363 #define S32_NVIC_IP_PRI289_MASK 0xFFu 1364 #define S32_NVIC_IP_PRI289_SHIFT 0u 1365 #define S32_NVIC_IP_PRI289_WIDTH 8u 1366 #define S32_NVIC_IP_PRI289(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI289_SHIFT))&S32_NVIC_IP_PRI289_MASK) 1367 #define S32_NVIC_IP_PRI289_MASK 0xFFu 1368 #define S32_NVIC_IP_PRI290_SHIFT 0u 1369 #define S32_NVIC_IP_PRI290_WIDTH 8u 1370 #define S32_NVIC_IP_PRI290(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI290_SHIFT))&S32_NVIC_IP_PRI290_MASK) 1371 #define S32_NVIC_IP_PRI290_MASK 0xFFu 1372 #define S32_NVIC_IP_PRI290_SHIFT 0u 1373 #define S32_NVIC_IP_PRI291_WIDTH 8u 1374 #define S32_NVIC_IP_PRI291(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI291_SHIFT))&S32_NVIC_IP_PRI291_MASK) 1375 #define S32_NVIC_IP_PRI291_MASK 0xFFu 1376 #define S32_NVIC_IP_PRI291_SHIFT 0u 1377 #define S32_NVIC_IP_PRI291_WIDTH 8u 1378 #define S32_NVIC_IP_PRI292(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI292_SHIFT))&S32_NVIC_IP_PRI292_MASK) 1379 #define S32_NVIC_IP_PRI292_MASK 0xFFu 1380 #define S32_NVIC_IP_PRI292_SHIFT 0u 1381 #define S32_NVIC_IP_PRI292_WIDTH 8u 1382 #define S32_NVIC_IP_PRI292(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI292_SHIFT))&S32_NVIC_IP_PRI292_MASK) 1383 #define S32_NVIC_IP_PRI293_MASK 0xFFu 1384 #define S32_NVIC_IP_PRI293_SHIFT 0u 1385 #define S32_NVIC_IP_PRI293_WIDTH 8u 1386 #define S32_NVIC_IP_PRI293(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI293_SHIFT))&S32_NVIC_IP_PRI293_MASK) 1387 #define S32_NVIC_IP_PRI293_MASK 0xFFu 1388 #define S32_NVIC_IP_PRI294_SHIFT 0u 1389 #define S32_NVIC_IP_PRI294_WIDTH 8u 1390 #define S32_NVIC_IP_PRI294(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI294_SHIFT))&S32_NVIC_IP_PRI294_MASK) 1391 #define S32_NVIC_IP_PRI294_MASK 0xFFu 1392 #define S32_NVIC_IP_PRI294_SHIFT 0u 1393 #define S32_NVIC_IP_PRI295_WIDTH 8u 1394 #define S32_NVIC_IP_PRI295(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI295_SHIFT))&S32_NVIC_IP_PRI295_MASK) 1395 #define S32_NVIC_IP_PRI295_MASK 0xFFu 1396 #define S32_NVIC_IP_PRI295_SHIFT 0u 1397 #define S32_NVIC_IP_PRI295_WIDTH 8u 1398 #define S32_NVIC_IP_PRI296(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI296_SHIFT))&S32_NVIC_IP_PRI296_MASK) 1399 #define S32_NVIC_IP_PRI296_MASK 0xFFu 1400 #define S32_NVIC_IP_PRI296_SHIFT 0u 1401 #define S32_NVIC_IP_PRI296_WIDTH 8u 1402 #define S32_NVIC_IP_PRI296(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI296_SHIFT))&S32_NVIC_IP_PRI296_MASK) 1403 #define S32_NVIC_IP_PRI297_MASK 0xFFu 1404 #define S32_NVIC_IP_PRI297_SHIFT 0u 1405 #define S32_NVIC_IP_PRI297_WIDTH 8u 1406 #define S32_NVIC_IP_PRI297(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI297_SHIFT))&S32_NVIC_IP_PRI297_MASK) 1407 #define S32_NVIC_IP_PRI297_MASK 0xFFu 1408 #define S32_NVIC_IP_PRI298_SHIFT 0u 1409 #define S32_NVIC_IP_PRI298_WIDTH 8u 1410 #define S32_NVIC_IP_PRI298(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI298_SHIFT))&S32_NVIC_IP_PRI298_MASK) 1411 #define S32_NVIC_IP_PRI298_MASK 0xFFu 1412 #define S32_NVIC_IP_PRI298_SHIFT 0u 1413 #define S32_NVIC_IP_PRI299_WIDTH 8u 1414 #define S32_NVIC_IP_PRI299(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI299_SHIFT))&S32_NVIC_IP_PRI299_MASK) 1415 #define S32_NVIC_IP_PRI299_MASK 0xFFu 1416 #define S32_NVIC_IP_PRI299_SHIFT 0u 1417 #define S32_NVIC_IP_PRI299_WIDTH 8u 1418 #define S32_NVIC_IP_PRI300(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI300_SHIFT))&S32_NVIC_IP_PRI300_MASK) 1419 #define S32_NVIC_IP_PRI300_MASK 0xFFu 1420 #define S32_NVIC_IP_PRI300_SHIFT 0u 1421 #define S32_NVIC_IP_PRI300_WIDTH 8u 1422 #define S32_NVIC_IP_PRI300(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI300_SHIFT))&S32_NVIC_IP_PRI300_MASK) 1423 #define S32_NVIC_IP_PRI301_MASK 0xFFu 1424 #define S32_NVIC_IP_PRI301_SHIFT 0u 1425 #define S32_NVIC_IP_PRI301_WIDTH 8u 1426 #define S32_NVIC_IP_PRI301(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI301_SHIFT))&S32_NVIC_IP_PRI301_MASK) 1427 #define S32_NVIC_IP_PRI301_MASK 0xFFu 1428 #define S32_NVIC_IP_PRI302_SHIFT 0u 1429 #define S32_NVIC_IP_PRI302_WIDTH 8u 1430 #define S32_NVIC_IP_PRI302(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI302_SHIFT))&S32_NVIC_IP_PRI302_MASK) 1431 #define S32_NVIC_IP_PRI302_MASK 0xFFu 1432 #define S32_NVIC_IP_PRI302_SHIFT 0u 1433 #define S32_NVIC_IP_PRI303_WIDTH 8u 1434 #define S32_NVIC_IP_PRI303(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI303_SHIFT))&S32_NVIC_IP_PRI303_MASK) 1435 #define S32_NVIC_IP_PRI303_MASK 0xFFu 1436 #define S32_NVIC_IP_PRI303_SHIFT 0u 1437 #define S32_NVIC_IP_PRI303_WIDTH 8u 1438 #define S32_NVIC_IP_PRI304(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI304_SHIFT))&S32_NVIC_IP_PRI304_MASK) 1439 #define S32_NVIC_IP_PRI304_MASK 0xFFu 1440 #define S32_NVIC_IP_PRI304_SHIFT 0u 1441 #define S32_NVIC_IP_PRI304_WIDTH 8u 1442 #define S32_NVIC_IP_PRI304(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI304_SHIFT))&S32_NVIC_IP_PRI304_MASK) 1443 #define S32_NVIC_IP_PRI305_MASK 0xFFu 1444 #define S32_NVIC_IP_PRI305_SHIFT 0u 1445 #define S32_NVIC_IP_PRI305_WIDTH 8u 1446 #define S32_NVIC_IP_PRI305(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI305_SHIFT))&S32_NVIC_IP_PRI305_MASK) 1447 #define S32_NVIC_IP_PRI305_MASK 0xFFu 1448 #define S32_NVIC_IP_PRI306_SHIFT 0u 1449 #define S32_NVIC_IP_PRI306_WIDTH 8u 1450 #define S32_NVIC_IP_PRI306(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI306_SHIFT))&S32_NVIC_IP_PRI306_MASK) 1451 #define S32_NVIC_IP_PRI306_MASK 0xFFu 1452 #define S32_NVIC_IP_PRI306_SHIFT 0u 1453 #define S32_NVIC_IP_PRI307_WIDTH 8u 1454 #define S32_NVIC_IP_PRI307(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI307_SHIFT))&S32_NVIC_IP_PRI307_MASK) 1455 #define S32_NVIC_IP_PRI307_MASK 0xFFu 1456 #define S32_NVIC_IP_PRI307_SHIFT 0u 1457 #define S32_NVIC_IP_PRI307_WIDTH 8u 1458 #define S32_NVIC_IP_PRI308(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI308_SHIFT))&S32_NVIC_IP_PRI308_MASK) 1459 #define S32_NVIC_IP_PRI308_MASK 0xFFu 1460 #define S32_NVIC_IP_PRI308_SHIFT 0u 1461 #define S32_NVIC_IP_PRI308_WIDTH 8u 1462 #define S32_NVIC_IP_PRI308(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI308_SHIFT))&S32_NVIC_IP_PRI308_MASK) 1463 #define S32_NVIC_IP_PRI309_MASK 0xFFu 1464 #define S32_NVIC_IP_PRI309_SHIFT 0u 1465 #define S32_NVIC_IP_PRI309_WIDTH 8u 1466 #define S32_NVIC_IP_PRI309(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI309_SHIFT))&S32_NVIC_IP_PRI309_MASK) 1467 #define S32_NVIC_IP_PRI309_MASK 0xFFu 1468 #define S32_NVIC_IP_PRI310_SHIFT 0u 1469 #define S32_NVIC_IP_PRI310_WIDTH 8u 1470 #define S32_NVIC_IP_PRI310(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI310_SHIFT))&S32_NVIC_IP_PRI310_MASK) 1471 #define S32_NVIC_IP_PRI310_MASK 0xFFu 1472 #define S32_NVIC_IP_PRI310_SHIFT 0u 1473 #define S32_NVIC_IP_PRI311_WIDTH 8u 1474 #define S32_NVIC_IP_PRI311(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI311_SHIFT))&S32_NVIC_IP_PRI311_MASK) 1475 #define S32_NVIC_IP_PRI311_MASK 0xFFu 1476 #define S32_NVIC_IP_PRI311_SHIFT 0u 1477 #define S32_NVIC_IP_PRI311_WIDTH 8u 1478 #define S32_NVIC_IP_PRI312(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI312_SHIFT))&S32_NVIC_IP_PRI312_MASK) 1479 #define S32_NVIC_IP_PRI312_MASK 0xFFu 1480 #define S32_NVIC_IP_PRI312_SHIFT 0u 1481 #define S32_NVIC_IP_PRI312_WIDTH 8u 1482 #define S32_NVIC_IP_PRI312(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI312_SHIFT))&S32_NVIC_IP_PRI312_MASK) 1483 #define S32_NVIC_IP_PRI313_MASK 0xFFu 1484 #define S32_NVIC_IP_PRI313_SHIFT 0u 1485 #define S32_NVIC_IP_PRI313_WIDTH 8u 1486 #define S32_NVIC_IP_PRI313(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI313_SHIFT))&S32_NVIC_IP_PRI313_MASK) 1487 #define S32_NVIC_IP_PRI313_MASK 0xFFu 1488 #define S32_NVIC_IP_PRI314_SHIFT 0u 1489 #define S32_NVIC_IP_PRI314_WIDTH 8u 1490 #define S32_NVIC_IP_PRI314(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI314_SHIFT))&S32_NVIC_IP_PRI314_MASK) 1491 #define S32_NVIC_IP_PRI314_MASK 0xFFu 1492 #define S32_NVIC_IP_PRI314_SHIFT 0u 1493 #define S32_NVIC_IP_PRI315_WIDTH 8u 1494 #define S32_NVIC_IP_PRI315(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI315_SHIFT))&S32_NVIC_IP_PRI315_MASK) 1495 #define S32_NVIC_IP_PRI315_MASK 0xFFu 1496 #define S32_NVIC_IP_PRI315_SHIFT 0u 1497 #define S32_NVIC_IP_PRI315_WIDTH 8u 1498 #define S32_NVIC_IP_PRI316(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI316_SHIFT))&S32_NVIC_IP_PRI316_MASK) 1499 #define S32_NVIC_IP_PRI316_MASK 0xFFu 1500 #define S32_NVIC_IP_PRI316_SHIFT 0u 1501 #define S32_NVIC_IP_PRI316_WIDTH 8u 1502 #define S32_NVIC_IP_PRI316(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI316_SHIFT))&S32_NVIC_IP_PRI316_MASK) 1503 #define S32_NVIC_IP_PRI317_MASK 0xFFu 1504 #define S32_NVIC_IP_PRI317_SHIFT 0u 1505 #define S32_NVIC_IP_PRI317_WIDTH 8u 1506 #define S32_NVIC_IP_PRI317(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI317_SHIFT))&S32_NVIC_IP_PRI317_MASK) 1507 #define S32_NVIC_IP_PRI317_MASK 0xFFu 1508 #define S32_NVIC_IP_PRI318_SHIFT 0u 1509 #define S32_NVIC_IP_PRI318_WIDTH 8u 1510 #define S32_NVIC_IP_PRI318(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI318_SHIFT))&S32_NVIC_IP_PRI318_MASK) 1511 #define S32_NVIC_IP_PRI318_MASK 0xFFu 1512 #define S32_NVIC_IP_PRI318_SHIFT 0u 1513 #define S32_NVIC_IP_PRI319_WIDTH 8u 1514 #define S32_NVIC_IP_PRI319(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI319_SHIFT))&S32_NVIC_IP_PRI319_MASK) 1515 #define S32_NVIC_IP_PRI319_MASK 0xFFu 1516 #define S32_NVIC_IP_PRI319_SHIFT 0u 1517 #define S32_NVIC_IP_PRI319_WIDTH 8u 1518 #define S32_NVIC_IP_PRI320(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI320_SHIFT))&S32_NVIC_IP_PRI320_MASK) 1519 #define S32_NVIC_IP_PRI320_MASK 0xFFu 1520 #define S32_NVIC_IP_PRI320_SHIFT 0u 1521 #define S32_NVIC_IP_PRI320_WIDTH 8u 1522 #define S32_NVIC_IP_PRI320(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI320_SHIFT))&S32_NVIC_IP_PRI320_MASK) 1523 #define S32_NVIC_IP_PRI321_MASK 0xFFu 1524 #define S32_NVIC_IP_PRI321_SHIFT 0u 1525 #define S32_NVIC_IP_PRI321_WIDTH 8u 1526 #define S32_NVIC_IP_PRI321(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI321_SHIFT))&S32_NVIC_IP_PRI321_MASK) 1527 #define S32_NVIC_IP_PRI321_MASK 0xFFu 1528 #define S32_NVIC_IP_PRI322_SHIFT 0u 1529 #define S32_NVIC_IP_PRI322_WIDTH 8u 1530 #define S32_NVIC_IP_PRI322(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI322_SHIFT))&S32_NVIC_IP_PRI322_MASK) 1531 #define S32_NVIC_IP_PRI322_MASK 0xFFu 1532 #define S32_NVIC_IP_PRI322_SHIFT 0u 1533 #define S32_NVIC_IP_PRI323_WIDTH 8u 1534 #define S32_NVIC_IP_PRI323(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI323_SHIFT))&S32_NVIC_IP_PRI323_MASK) 1535 #define S32_NVIC_IP_PRI323_MASK 0xFFu 1536 #define S32_NVIC_IP_PRI323_SHIFT 0u 1537 #define S32_NVIC_IP_PRI323_WIDTH 8u 1538 #define S32_NVIC_IP_PRI324(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI324_SHIFT))&S32_NVIC_IP_PRI324_MASK) 1539 #define S32_NVIC_IP_PRI324_MASK 0xFFu 1540 #define S32_NVIC_IP_PRI324_SHIFT 0u 1541 #define S32_NVIC_IP_PRI324_WIDTH 8u 1542 #define S32_NVIC_IP_PRI324(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI324_SHIFT))&S32_NVIC_IP_PRI324_MASK) 1543 #define S32_NVIC_IP_PRI325_MASK 0xFFu 1544 #define S32_NVIC_IP_PRI325_SHIFT 0u 1545 #define S32_NVIC_IP_PRI325_WIDTH 8u 1546 #define S32_NVIC_IP_PRI325(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI325_SHIFT))&S32_NVIC_IP_PRI325_MASK) 1547 #define S32_NVIC_IP_PRI325_MASK 0xFFu 1548 #define S32_NVIC_IP_PRI326_SHIFT 0u 1549 #define S32_NVIC_IP_PRI326_WIDTH 8u 1550 #define S32_NVIC_IP_PRI326(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI326_SHIFT))&S32_NVIC_IP_PRI326_MASK) 1551 #define S32_NVIC_IP_PRI326_MASK 0xFFu 1552 #define S32_NVIC_IP_PRI326_SHIFT 0u 1553 #define S32_NVIC_IP_PRI327_WIDTH 8u 1554 #define S32_NVIC_IP_PRI327(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI327_SHIFT))&S32_NVIC_IP_PRI327_MASK) 1555 #define S32_NVIC_IP_PRI327_MASK 0xFFu 1556 #define S32_NVIC_IP_PRI327_SHIFT 0u 1557 #define S32_NVIC_IP_PRI327_WIDTH 8u 1558 #define S32_NVIC_IP_PRI328(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI328_SHIFT))&S32_NVIC_IP_PRI328_MASK) 1559 #define S32_NVIC_IP_PRI328_MASK 0xFFu 1560 #define S32_NVIC_IP_PRI328_SHIFT 0u 1561 #define S32_NVIC_IP_PRI328_WIDTH 8u 1562 #define S32_NVIC_IP_PRI328(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI328_SHIFT))&S32_NVIC_IP_PRI328_MASK) 1563 #define S32_NVIC_IP_PRI329_MASK 0xFFu 1564 #define S32_NVIC_IP_PRI329_SHIFT 0u 1565 #define S32_NVIC_IP_PRI329_WIDTH 8u 1566 #define S32_NVIC_IP_PRI329(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI329_SHIFT))&S32_NVIC_IP_PRI329_MASK) 1567 #define S32_NVIC_IP_PRI329_MASK 0xFFu 1568 #define S32_NVIC_IP_PRI330_SHIFT 0u 1569 #define S32_NVIC_IP_PRI330_WIDTH 8u 1570 #define S32_NVIC_IP_PRI330(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI330_SHIFT))&S32_NVIC_IP_PRI330_MASK) 1571 #define S32_NVIC_IP_PRI330_MASK 0xFFu 1572 #define S32_NVIC_IP_PRI330_SHIFT 0u 1573 #define S32_NVIC_IP_PRI331_WIDTH 8u 1574 #define S32_NVIC_IP_PRI331(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI331_SHIFT))&S32_NVIC_IP_PRI331_MASK) 1575 #define S32_NVIC_IP_PRI331_MASK 0xFFu 1576 #define S32_NVIC_IP_PRI331_SHIFT 0u 1577 #define S32_NVIC_IP_PRI331_WIDTH 8u 1578 #define S32_NVIC_IP_PRI332(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI332_SHIFT))&S32_NVIC_IP_PRI332_MASK) 1579 #define S32_NVIC_IP_PRI332_MASK 0xFFu 1580 #define S32_NVIC_IP_PRI332_SHIFT 0u 1581 #define S32_NVIC_IP_PRI332_WIDTH 8u 1582 #define S32_NVIC_IP_PRI332(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI332_SHIFT))&S32_NVIC_IP_PRI332_MASK) 1583 #define S32_NVIC_IP_PRI333_MASK 0xFFu 1584 #define S32_NVIC_IP_PRI333_SHIFT 0u 1585 #define S32_NVIC_IP_PRI333_WIDTH 8u 1586 #define S32_NVIC_IP_PRI333(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI333_SHIFT))&S32_NVIC_IP_PRI333_MASK) 1587 #define S32_NVIC_IP_PRI333_MASK 0xFFu 1588 #define S32_NVIC_IP_PRI334_SHIFT 0u 1589 #define S32_NVIC_IP_PRI334_WIDTH 8u 1590 #define S32_NVIC_IP_PRI334(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI334_SHIFT))&S32_NVIC_IP_PRI334_MASK) 1591 #define S32_NVIC_IP_PRI334_MASK 0xFFu 1592 #define S32_NVIC_IP_PRI334_SHIFT 0u 1593 #define S32_NVIC_IP_PRI335_WIDTH 8u 1594 #define S32_NVIC_IP_PRI335(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI335_SHIFT))&S32_NVIC_IP_PRI335_MASK) 1595 #define S32_NVIC_IP_PRI335_MASK 0xFFu 1596 #define S32_NVIC_IP_PRI335_SHIFT 0u 1597 #define S32_NVIC_IP_PRI335_WIDTH 8u 1598 #define S32_NVIC_IP_PRI336(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI336_SHIFT))&S32_NVIC_IP_PRI336_MASK) 1599 #define S32_NVIC_IP_PRI336_MASK 0xFFu 1600 #define S32_NVIC_IP_PRI336_SHIFT 0u 1601 #define S32_NVIC_IP_PRI336_WIDTH 8u 1602 #define S32_NVIC_IP_PRI336(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI336_SHIFT))&S32_NVIC_IP_PRI336_MASK) 1603 #define S32_NVIC_IP_PRI337_MASK 0xFFu 1604 #define S32_NVIC_IP_PRI337_SHIFT 0u 1605 #define S32_NVIC_IP_PRI337_WIDTH 8u 1606 #define S32_NVIC_IP_PRI337(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI337_SHIFT))&S32_NVIC_IP_PRI337_MASK) 1607 #define S32_NVIC_IP_PRI337_MASK 0xFFu 1608 #define S32_NVIC_IP_PRI338_SHIFT 0u 1609 #define S32_NVIC_IP_PRI338_WIDTH 8u 1610 #define S32_NVIC_IP_PRI338(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI338_SHIFT))&S32_NVIC_IP_PRI338_MASK) 1611 #define S32_NVIC_IP_PRI338_MASK 0xFFu 1612 #define S32_NVIC_IP_PRI338_SHIFT 0u 1613 #define S32_NVIC_IP_PRI339_WIDTH 8u 1614 #define S32_NVIC_IP_PRI339(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI339_SHIFT))&S32_NVIC_IP_PRI339_MASK) 1615 #define S32_NVIC_IP_PRI339_MASK 0xFFu 1616 #define S32_NVIC_IP_PRI339_SHIFT 0u 1617 #define S32_NVIC_IP_PRI339_WIDTH 8u 1618 #define S32_NVIC_IP_PRI340(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI340_SHIFT))&S32_NVIC_IP_PRI340_MASK) 1619 #define S32_NVIC_IP_PRI340_MASK 0xFFu 1620 #define S32_NVIC_IP_PRI340_SHIFT 0u 1621 #define S32_NVIC_IP_PRI340_WIDTH 8u 1622 #define S32_NVIC_IP_PRI340(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI340_SHIFT))&S32_NVIC_IP_PRI340_MASK) 1623 #define S32_NVIC_IP_PRI341_MASK 0xFFu 1624 #define S32_NVIC_IP_PRI341_SHIFT 0u 1625 #define S32_NVIC_IP_PRI341_WIDTH 8u 1626 #define S32_NVIC_IP_PRI341(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI341_SHIFT))&S32_NVIC_IP_PRI341_MASK) 1627 #define S32_NVIC_IP_PRI341_MASK 0xFFu 1628 #define S32_NVIC_IP_PRI342_SHIFT 0u 1629 #define S32_NVIC_IP_PRI342_WIDTH 8u 1630 #define S32_NVIC_IP_PRI342(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI342_SHIFT))&S32_NVIC_IP_PRI342_MASK) 1631 #define S32_NVIC_IP_PRI342_MASK 0xFFu 1632 #define S32_NVIC_IP_PRI342_SHIFT 0u 1633 #define S32_NVIC_IP_PRI343_WIDTH 8u 1634 #define S32_NVIC_IP_PRI343(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI343_SHIFT))&S32_NVIC_IP_PRI343_MASK) 1635 #define S32_NVIC_IP_PRI343_MASK 0xFFu 1636 #define S32_NVIC_IP_PRI343_SHIFT 0u 1637 #define S32_NVIC_IP_PRI343_WIDTH 8u 1638 #define S32_NVIC_IP_PRI344(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI344_SHIFT))&S32_NVIC_IP_PRI344_MASK) 1639 #define S32_NVIC_IP_PRI344_MASK 0xFFu 1640 #define S32_NVIC_IP_PRI344_SHIFT 0u 1641 #define S32_NVIC_IP_PRI344_WIDTH 8u 1642 #define S32_NVIC_IP_PRI344(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI344_SHIFT))&S32_NVIC_IP_PRI344_MASK) 1643 #define S32_NVIC_IP_PRI345_MASK 0xFFu 1644 #define S32_NVIC_IP_PRI345_SHIFT 0u 1645 #define S32_NVIC_IP_PRI345_WIDTH 8u 1646 #define S32_NVIC_IP_PRI345(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI345_SHIFT))&S32_NVIC_IP_PRI345_MASK) 1647 #define S32_NVIC_IP_PRI345_MASK 0xFFu 1648 #define S32_NVIC_IP_PRI346_SHIFT 0u 1649 #define S32_NVIC_IP_PRI346_WIDTH 8u 1650 #define S32_NVIC_IP_PRI346(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI346_SHIFT))&S32_NVIC_IP_PRI346_MASK) 1651 #define S32_NVIC_IP_PRI346_MASK 0xFFu 1652 #define S32_NVIC_IP_PRI346_SHIFT 0u 1653 #define S32_NVIC_IP_PRI347_WIDTH 8u 1654 #define S32_NVIC_IP_PRI347(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI347_SHIFT))&S32_NVIC_IP_PRI347_MASK) 1655 #define S32_NVIC_IP_PRI347_MASK 0xFFu 1656 #define S32_NVIC_IP_PRI347_SHIFT 0u 1657 #define S32_NVIC_IP_PRI347_WIDTH 8u 1658 #define S32_NVIC_IP_PRI348(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI348_SHIFT))&S32_NVIC_IP_PRI348_MASK) 1659 #define S32_NVIC_IP_PRI348_MASK 0xFFu 1660 #define S32_NVIC_IP_PRI348_SHIFT 0u 1661 #define S32_NVIC_IP_PRI348_WIDTH 8u 1662 #define S32_NVIC_IP_PRI348(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI348_SHIFT))&S32_NVIC_IP_PRI348_MASK) 1663 #define S32_NVIC_IP_PRI349_MASK 0xFFu 1664 #define S32_NVIC_IP_PRI349_SHIFT 0u 1665 #define S32_NVIC_IP_PRI349_WIDTH 8u 1666 #define S32_NVIC_IP_PRI349(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI349_SHIFT))&S32_NVIC_IP_PRI349_MASK) 1667 #define S32_NVIC_IP_PRI349_MASK 0xFFu 1668 #define S32_NVIC_IP_PRI350_SHIFT 0u 1669 #define S32_NVIC_IP_PRI350_WIDTH 8u 1670 #define S32_NVIC_IP_PRI350(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI350_SHIFT))&S32_NVIC_IP_PRI350_MASK) 1671 #define S32_NVIC_IP_PRI350_MASK 0xFFu 1672 #define S32_NVIC_IP_PRI350_SHIFT 0u 1673 #define S32_NVIC_IP_PRI351_WIDTH 8u 1674 #define S32_NVIC_IP_PRI351(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI351_SHIFT))&S32_NVIC_IP_PRI351_MASK) 1675 #define S32_NVIC_IP_PRI351_MASK 0xFFu 1676 #define S32_NVIC_IP_PRI351_SHIFT 0u 1677 #define S32_NVIC_IP_PRI351_WIDTH 8u 1678 #define S32_NVIC_IP_PRI352(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI352_SHIFT))&S32_NVIC_IP_PRI352_MASK) 1679 #define S32_NVIC_IP_PRI352_MASK 0xFFu 1680 #define S32_NVIC_IP_PRI352_SHIFT 0u 1681 #define S32_NVIC_IP_PRI352_WIDTH 8u 1682 #define S32_NVIC_IP_PRI352(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI352_SHIFT))&S32_NVIC_IP_PRI352_MASK) 1683 #define S32_NVIC_IP_PRI353_MASK 0xFFu 1684 #define S32_NVIC_IP_PRI353_SHIFT 0u 1685 #define S32_NVIC_IP_PRI353_WIDTH 8u 1686 #define S32_NVIC_IP_PRI353(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI353_SHIFT))&S32_NVIC_IP_PRI353_MASK) 1687 #define S32_NVIC_IP_PRI353_MASK 0xFFu 1688 #define S32_NVIC_IP_PRI354_SHIFT 0u 1689 #define S32_NVIC_IP_PRI354_WIDTH 8u 1690 #define S32_NVIC_IP_PRI354(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI354_SHIFT))&S32_NVIC_IP_PRI354_MASK) 1691 #define S32_NVIC_IP_PRI354_MASK 0xFFu 1692 #define S32_NVIC_IP_PRI354_SHIFT 0u 1693 #define S32_NVIC_IP_PRI355_WIDTH 8u 1694 #define S32_NVIC_IP_PRI355(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI355_SHIFT))&S32_NVIC_IP_PRI355_MASK) 1695 #define S32_NVIC_IP_PRI355_MASK 0xFFu 1696 #define S32_NVIC_IP_PRI355_SHIFT 0u 1697 #define S32_NVIC_IP_PRI355_WIDTH 8u 1698 #define S32_NVIC_IP_PRI356(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI356_SHIFT))&S32_NVIC_IP_PRI356_MASK) 1699 #define S32_NVIC_IP_PRI356_MASK 0xFFu 1700 #define S32_NVIC_IP_PRI356_SHIFT 0u 1701 #define S32_NVIC_IP_PRI356_WIDTH 8u 1702 #define S32_NVIC_IP_PRI356(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI356_SHIFT))&S32_NVIC_IP_PRI356_MASK) 1703 #define S32_NVIC_IP_PRI357_MASK 0xFFu 1704 #define S32_NVIC_IP_PRI357_SHIFT 0u 1705 #define S32_NVIC_IP_PRI357_WIDTH 8u 1706 #define S32_NVIC_IP_PRI357(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI357_SHIFT))&S32_NVIC_IP_PRI357_MASK) 1707 #define S32_NVIC_IP_PRI357_MASK 0xFFu 1708 #define S32_NVIC_IP_PRI358_SHIFT 0u 1709 #define S32_NVIC_IP_PRI358_WIDTH 8u 1710 #define S32_NVIC_IP_PRI358(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI358_SHIFT))&S32_NVIC_IP_PRI358_MASK) 1711 #define S32_NVIC_IP_PRI358_MASK 0xFFu 1712 #define S32_NVIC_IP_PRI358_SHIFT 0u 1713 #define S32_NVIC_IP_PRI359_WIDTH 8u 1714 #define S32_NVIC_IP_PRI359(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI359_SHIFT))&S32_NVIC_IP_PRI359_MASK) 1715 #define S32_NVIC_IP_PRI359_MASK 0xFFu 1716 #define S32_NVIC_IP_PRI359_SHIFT 0u 1717 #define S32_NVIC_IP_PRI359_WIDTH 8u 1718 #define S32_NVIC_IP_PRI360(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI360_SHIFT))&S32_NVIC_IP_PRI360_MASK) 1719 #define S32_NVIC_IP_PRI360_MASK 0xFFu 1720 #define S32_NVIC_IP_PRI360_SHIFT 0u 1721 #define S32_NVIC_IP_PRI360_WIDTH 8u 1722 #define S32_NVIC_IP_PRI360(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI360_SHIFT))&S32_NVIC_IP_PRI360_MASK) 1723 #define S32_NVIC_IP_PRI361_MASK 0xFFu 1724 #define S32_NVIC_IP_PRI361_SHIFT 0u 1725 #define S32_NVIC_IP_PRI361_WIDTH 8u 1726 #define S32_NVIC_IP_PRI361(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI361_SHIFT))&S32_NVIC_IP_PRI361_MASK) 1727 #define S32_NVIC_IP_PRI361_MASK 0xFFu 1728 #define S32_NVIC_IP_PRI362_SHIFT 0u 1729 #define S32_NVIC_IP_PRI362_WIDTH 8u 1730 #define S32_NVIC_IP_PRI362(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI362_SHIFT))&S32_NVIC_IP_PRI362_MASK) 1731 #define S32_NVIC_IP_PRI362_MASK 0xFFu 1732 #define S32_NVIC_IP_PRI362_SHIFT 0u 1733 #define S32_NVIC_IP_PRI363_WIDTH 8u 1734 #define S32_NVIC_IP_PRI363(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI363_SHIFT))&S32_NVIC_IP_PRI363_MASK) 1735 #define S32_NVIC_IP_PRI363_MASK 0xFFu 1736 #define S32_NVIC_IP_PRI363_SHIFT 0u 1737 #define S32_NVIC_IP_PRI363_WIDTH 8u 1738 #define S32_NVIC_IP_PRI364(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI364_SHIFT))&S32_NVIC_IP_PRI364_MASK) 1739 #define S32_NVIC_IP_PRI364_MASK 0xFFu 1740 #define S32_NVIC_IP_PRI364_SHIFT 0u 1741 #define S32_NVIC_IP_PRI364_WIDTH 8u 1742 #define S32_NVIC_IP_PRI364(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI364_SHIFT))&S32_NVIC_IP_PRI364_MASK) 1743 #define S32_NVIC_IP_PRI365_MASK 0xFFu 1744 #define S32_NVIC_IP_PRI365_SHIFT 0u 1745 #define S32_NVIC_IP_PRI365_WIDTH 8u 1746 #define S32_NVIC_IP_PRI365(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI365_SHIFT))&S32_NVIC_IP_PRI365_MASK) 1747 #define S32_NVIC_IP_PRI365_MASK 0xFFu 1748 #define S32_NVIC_IP_PRI366_SHIFT 0u 1749 #define S32_NVIC_IP_PRI366_WIDTH 8u 1750 #define S32_NVIC_IP_PRI366(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI366_SHIFT))&S32_NVIC_IP_PRI366_MASK) 1751 #define S32_NVIC_IP_PRI366_MASK 0xFFu 1752 #define S32_NVIC_IP_PRI366_SHIFT 0u 1753 #define S32_NVIC_IP_PRI367_WIDTH 8u 1754 #define S32_NVIC_IP_PRI367(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI367_SHIFT))&S32_NVIC_IP_PRI367_MASK) 1755 #define S32_NVIC_IP_PRI367_MASK 0xFFu 1756 #define S32_NVIC_IP_PRI367_SHIFT 0u 1757 #define S32_NVIC_IP_PRI367_WIDTH 8u 1758 #define S32_NVIC_IP_PRI368(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI368_SHIFT))&S32_NVIC_IP_PRI368_MASK) 1759 #define S32_NVIC_IP_PRI368_MASK 0xFFu 1760 #define S32_NVIC_IP_PRI368_SHIFT 0u 1761 #define S32_NVIC_IP_PRI368_WIDTH 8u 1762 #define S32_NVIC_IP_PRI368(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI368_SHIFT))&S32_NVIC_IP_PRI368_MASK) 1763 #define S32_NVIC_IP_PRI369_MASK 0xFFu 1764 #define S32_NVIC_IP_PRI369_SHIFT 0u 1765 #define S32_NVIC_IP_PRI369_WIDTH 8u 1766 #define S32_NVIC_IP_PRI369(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI369_SHIFT))&S32_NVIC_IP_PRI369_MASK) 1767 #define S32_NVIC_IP_PRI369_MASK 0xFFu 1768 #define S32_NVIC_IP_PRI370_SHIFT 0u 1769 #define S32_NVIC_IP_PRI370_WIDTH 8u 1770 #define S32_NVIC_IP_PRI370(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI370_SHIFT))&S32_NVIC_IP_PRI370_MASK) 1771 #define S32_NVIC_IP_PRI370_MASK 0xFFu 1772 #define S32_NVIC_IP_PRI370_SHIFT 0u 1773 #define S32_NVIC_IP_PRI371_WIDTH 8u 1774 #define S32_NVIC_IP_PRI371(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI371_SHIFT))&S32_NVIC_IP_PRI371_MASK) 1775 #define S32_NVIC_IP_PRI371_MASK 0xFFu 1776 #define S32_NVIC_IP_PRI371_SHIFT 0u 1777 #define S32_NVIC_IP_PRI371_WIDTH 8u 1778 #define S32_NVIC_IP_PRI372(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI372_SHIFT))&S32_NVIC_IP_PRI372_MASK) 1779 #define S32_NVIC_IP_PRI372_MASK 0xFFu 1780 #define S32_NVIC_IP_PRI372_SHIFT 0u 1781 #define S32_NVIC_IP_PRI372_WIDTH 8u 1782 #define S32_NVIC_IP_PRI372(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI372_SHIFT))&S32_NVIC_IP_PRI372_MASK) 1783 #define S32_NVIC_IP_PRI373_MASK 0xFFu 1784 #define S32_NVIC_IP_PRI373_SHIFT 0u 1785 #define S32_NVIC_IP_PRI373_WIDTH 8u 1786 #define S32_NVIC_IP_PRI373(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI373_SHIFT))&S32_NVIC_IP_PRI373_MASK) 1787 #define S32_NVIC_IP_PRI373_MASK 0xFFu 1788 #define S32_NVIC_IP_PRI374_SHIFT 0u 1789 #define S32_NVIC_IP_PRI374_WIDTH 8u 1790 #define S32_NVIC_IP_PRI374(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI374_SHIFT))&S32_NVIC_IP_PRI374_MASK) 1791 #define S32_NVIC_IP_PRI374_MASK 0xFFu 1792 #define S32_NVIC_IP_PRI374_SHIFT 0u 1793 #define S32_NVIC_IP_PRI375_WIDTH 8u 1794 #define S32_NVIC_IP_PRI375(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI375_SHIFT))&S32_NVIC_IP_PRI375_MASK) 1795 #define S32_NVIC_IP_PRI375_MASK 0xFFu 1796 #define S32_NVIC_IP_PRI375_SHIFT 0u 1797 #define S32_NVIC_IP_PRI375_WIDTH 8u 1798 #define S32_NVIC_IP_PRI376(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI376_SHIFT))&S32_NVIC_IP_PRI376_MASK) 1799 #define S32_NVIC_IP_PRI376_MASK 0xFFu 1800 #define S32_NVIC_IP_PRI376_SHIFT 0u 1801 #define S32_NVIC_IP_PRI376_WIDTH 8u 1802 #define S32_NVIC_IP_PRI376(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI376_SHIFT))&S32_NVIC_IP_PRI376_MASK) 1803 #define S32_NVIC_IP_PRI377_MASK 0xFFu 1804 #define S32_NVIC_IP_PRI377_SHIFT 0u 1805 #define S32_NVIC_IP_PRI377_WIDTH 8u 1806 #define S32_NVIC_IP_PRI377(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI377_SHIFT))&S32_NVIC_IP_PRI377_MASK) 1807 #define S32_NVIC_IP_PRI377_MASK 0xFFu 1808 #define S32_NVIC_IP_PRI378_SHIFT 0u 1809 #define S32_NVIC_IP_PRI378_WIDTH 8u 1810 #define S32_NVIC_IP_PRI378(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI378_SHIFT))&S32_NVIC_IP_PRI378_MASK) 1811 #define S32_NVIC_IP_PRI378_MASK 0xFFu 1812 #define S32_NVIC_IP_PRI378_SHIFT 0u 1813 #define S32_NVIC_IP_PRI379_WIDTH 8u 1814 #define S32_NVIC_IP_PRI379(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI379_SHIFT))&S32_NVIC_IP_PRI379_MASK) 1815 #define S32_NVIC_IP_PRI379_MASK 0xFFu 1816 #define S32_NVIC_IP_PRI379_SHIFT 0u 1817 #define S32_NVIC_IP_PRI379_WIDTH 8u 1818 #define S32_NVIC_IP_PRI380(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI380_SHIFT))&S32_NVIC_IP_PRI380_MASK) 1819 #define S32_NVIC_IP_PRI380_MASK 0xFFu 1820 #define S32_NVIC_IP_PRI380_SHIFT 0u 1821 #define S32_NVIC_IP_PRI380_WIDTH 8u 1822 #define S32_NVIC_IP_PRI380(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI380_SHIFT))&S32_NVIC_IP_PRI380_MASK) 1823 #define S32_NVIC_IP_PRI381_MASK 0xFFu 1824 #define S32_NVIC_IP_PRI381_SHIFT 0u 1825 #define S32_NVIC_IP_PRI381_WIDTH 8u 1826 #define S32_NVIC_IP_PRI381(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI381_SHIFT))&S32_NVIC_IP_PRI381_MASK) 1827 #define S32_NVIC_IP_PRI381_MASK 0xFFu 1828 #define S32_NVIC_IP_PRI382_SHIFT 0u 1829 #define S32_NVIC_IP_PRI382_WIDTH 8u 1830 #define S32_NVIC_IP_PRI382(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI382_SHIFT))&S32_NVIC_IP_PRI382_MASK) 1831 #define S32_NVIC_IP_PRI382_MASK 0xFFu 1832 #define S32_NVIC_IP_PRI382_SHIFT 0u 1833 #define S32_NVIC_IP_PRI383_WIDTH 8u 1834 #define S32_NVIC_IP_PRI383(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI383_SHIFT))&S32_NVIC_IP_PRI383_MASK) 1835 #define S32_NVIC_IP_PRI383_MASK 0xFFu 1836 #define S32_NVIC_IP_PRI383_SHIFT 0u 1837 #define S32_NVIC_IP_PRI383_WIDTH 8u 1838 #define S32_NVIC_IP_PRI384(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI384_SHIFT))&S32_NVIC_IP_PRI384_MASK) 1839 #define S32_NVIC_IP_PRI384_MASK 0xFFu 1840 #define S32_NVIC_IP_PRI384_SHIFT 0u 1841 #define S32_NVIC_IP_PRI384_WIDTH 8u 1842 #define S32_NVIC_IP_PRI384(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI384_SHIFT))&S32_NVIC_IP_PRI384_MASK) 1843 #define S32_NVIC_IP_PRI385_MASK 0xFFu 1844 #define S32_NVIC_IP_PRI385_SHIFT 0u 1845 #define S32_NVIC_IP_PRI385_WIDTH 8u 1846 #define S32_NVIC_IP_PRI385(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI385_SHIFT))&S32_NVIC_IP_PRI385_MASK) 1847 #define S32_NVIC_IP_PRI385_MASK 0xFFu 1848 #define S32_NVIC_IP_PRI386_SHIFT 0u 1849 #define S32_NVIC_IP_PRI386_WIDTH 8u 1850 #define S32_NVIC_IP_PRI386(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI386_SHIFT))&S32_NVIC_IP_PRI386_MASK) 1851 #define S32_NVIC_IP_PRI386_MASK 0xFFu 1852 #define S32_NVIC_IP_PRI386_SHIFT 0u 1853 #define S32_NVIC_IP_PRI387_WIDTH 8u 1854 #define S32_NVIC_IP_PRI387(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI387_SHIFT))&S32_NVIC_IP_PRI387_MASK) 1855 #define S32_NVIC_IP_PRI387_MASK 0xFFu 1856 #define S32_NVIC_IP_PRI387_SHIFT 0u 1857 #define S32_NVIC_IP_PRI387_WIDTH 8u 1858 #define S32_NVIC_IP_PRI388(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI388_SHIFT))&S32_NVIC_IP_PRI388_MASK) 1859 #define S32_NVIC_IP_PRI388_MASK 0xFFu 1860 #define S32_NVIC_IP_PRI388_SHIFT 0u 1861 #define S32_NVIC_IP_PRI388_WIDTH 8u 1862 #define S32_NVIC_IP_PRI388(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI388_SHIFT))&S32_NVIC_IP_PRI388_MASK) 1863 #define S32_NVIC_IP_PRI389_MASK 0xFFu 1864 #define S32_NVIC_IP_PRI389_SHIFT 0u 1865 #define S32_NVIC_IP_PRI389_WIDTH 8u 1866 #define S32_NVIC_IP_PRI389(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI389_SHIFT))&S32_NVIC_IP_PRI389_MASK) 1867 #define S32_NVIC_IP_PRI389_MASK 0xFFu 1868 #define S32_NVIC_IP_PRI390_SHIFT 0u 1869 #define S32_NVIC_IP_PRI390_WIDTH 8u 1870 #define S32_NVIC_IP_PRI390(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI390_SHIFT))&S32_NVIC_IP_PRI390_MASK) 1871 #define S32_NVIC_IP_PRI390_MASK 0xFFu 1872 #define S32_NVIC_IP_PRI390_SHIFT 0u 1873 #define S32_NVIC_IP_PRI391_WIDTH 8u 1874 #define S32_NVIC_IP_PRI391(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI391_SHIFT))&S32_NVIC_IP_PRI391_MASK) 1875 #define S32_NVIC_IP_PRI391_MASK 0xFFu 1876 #define S32_NVIC_IP_PRI391_SHIFT 0u 1877 #define S32_NVIC_IP_PRI391_WIDTH 8u 1878 #define S32_NVIC_IP_PRI392(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI392_SHIFT))&S32_NVIC_IP_PRI392_MASK) 1879 #define S32_NVIC_IP_PRI392_MASK 0xFFu 1880 #define S32_NVIC_IP_PRI392_SHIFT 0u 1881 #define S32_NVIC_IP_PRI392_WIDTH 8u 1882 #define S32_NVIC_IP_PRI392(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI392_SHIFT))&S32_NVIC_IP_PRI392_MASK) 1883 #define S32_NVIC_IP_PRI393_MASK 0xFFu 1884 #define S32_NVIC_IP_PRI393_SHIFT 0u 1885 #define S32_NVIC_IP_PRI393_WIDTH 8u 1886 #define S32_NVIC_IP_PRI393(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI393_SHIFT))&S32_NVIC_IP_PRI393_MASK) 1887 #define S32_NVIC_IP_PRI393_MASK 0xFFu 1888 #define S32_NVIC_IP_PRI394_SHIFT 0u 1889 #define S32_NVIC_IP_PRI394_WIDTH 8u 1890 #define S32_NVIC_IP_PRI394(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI394_SHIFT))&S32_NVIC_IP_PRI394_MASK) 1891 #define S32_NVIC_IP_PRI394_MASK 0xFFu 1892 #define S32_NVIC_IP_PRI394_SHIFT 0u 1893 #define S32_NVIC_IP_PRI395_WIDTH 8u 1894 #define S32_NVIC_IP_PRI395(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI395_SHIFT))&S32_NVIC_IP_PRI395_MASK) 1895 #define S32_NVIC_IP_PRI395_MASK 0xFFu 1896 #define S32_NVIC_IP_PRI395_SHIFT 0u 1897 #define S32_NVIC_IP_PRI395_WIDTH 8u 1898 #define S32_NVIC_IP_PRI396(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI396_SHIFT))&S32_NVIC_IP_PRI396_MASK) 1899 #define S32_NVIC_IP_PRI396_MASK 0xFFu 1900 #define S32_NVIC_IP_PRI396_SHIFT 0u 1901 #define S32_NVIC_IP_PRI396_WIDTH 8u 1902 #define S32_NVIC_IP_PRI396(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI396_SHIFT))&S32_NVIC_IP_PRI396_MASK) 1903 #define S32_NVIC_IP_PRI397_MASK 0xFFu 1904 #define S32_NVIC_IP_PRI397_SHIFT 0u 1905 #define S32_NVIC_IP_PRI397_WIDTH 8u 1906 #define S32_NVIC_IP_PRI397(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI397_SHIFT))&S32_NVIC_IP_PRI397_MASK) 1907 #define S32_NVIC_IP_PRI397_MASK 0xFFu 1908 #define S32_NVIC_IP_PRI398_SHIFT 0u 1909 #define S32_NVIC_IP_PRI398_WIDTH 8u 1910 #define S32_NVIC_IP_PRI398(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI398_SHIFT))&S32_NVIC_IP_PRI398_MASK) 1911 #define S32_NVIC_IP_PRI398_MASK 0xFFu 1912 #define S32_NVIC_IP_PRI398_SHIFT 0u 1913 #define S32_NVIC_IP_PRI399_WIDTH 8u 1914 #define S32_NVIC_IP_PRI399(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI399_SHIFT))&S32_NVIC_IP_PRI399_MASK) 1915 #define S32_NVIC_IP_PRI399_MASK 0xFFu 1916 #define S32_NVIC_IP_PRI399_SHIFT 0u 1917 #define S32_NVIC_IP_PRI399_WIDTH 8u 1918 #define S32_NVIC_IP_PRI400(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI400_SHIFT))&S32_NVIC_IP_PRI400_MASK) 1919 #define S32_NVIC_IP_PRI400_MASK 0xFFu 1920 #define S32_NVIC_IP_PRI400_SHIFT 0u 1921 #define S32_NVIC_IP_PRI400_WIDTH 8u 1922 #define S32_NVIC_IP_PRI400(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI400_SHIFT))&S32_NVIC_IP_PRI400_MASK) 1923 #define S32_NVIC_IP_PRI401_MASK 0xFFu 1924 #define S32_NVIC_IP_PRI401_SHIFT 0u 1925 #define S32_NVIC_IP_PRI401_WIDTH 8u 1926 #define S32_NVIC_IP_PRI401(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI401_SHIFT))&S32_NVIC_IP_PRI401_MASK) 1927 #define S32_NVIC_IP_PRI401_MASK 0xFFu 1928 #define S32_NVIC_IP_PRI402_SHIFT 0u 1929 #define S32_NVIC_IP_PRI402_WIDTH 8u 1930 #define S32_NVIC_IP_PRI402(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI402_SHIFT))&S32_NVIC_IP_PRI402_MASK) 1931 #define S32_NVIC_IP_PRI402_MASK 0xFFu 1932 #define S32_NVIC_IP_PRI402_SHIFT 0u 1933 #define S32_NVIC_IP_PRI403_WIDTH 8u 1934 #define S32_NVIC_IP_PRI403(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI403_SHIFT))&S32_NVIC_IP_PRI403_MASK) 1935 #define S32_NVIC_IP_PRI403_MASK 0xFFu 1936 #define S32_NVIC_IP_PRI403_SHIFT 0u 1937 #define S32_NVIC_IP_PRI403_WIDTH 8u 1938 #define S32_NVIC_IP_PRI404(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI404_SHIFT))&S32_NVIC_IP_PRI404_MASK) 1939 #define S32_NVIC_IP_PRI404_MASK 0xFFu 1940 #define S32_NVIC_IP_PRI404_SHIFT 0u 1941 #define S32_NVIC_IP_PRI404_WIDTH 8u 1942 #define S32_NVIC_IP_PRI404(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI404_SHIFT))&S32_NVIC_IP_PRI404_MASK) 1943 #define S32_NVIC_IP_PRI405_MASK 0xFFu 1944 #define S32_NVIC_IP_PRI405_SHIFT 0u 1945 #define S32_NVIC_IP_PRI405_WIDTH 8u 1946 #define S32_NVIC_IP_PRI405(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI405_SHIFT))&S32_NVIC_IP_PRI405_MASK) 1947 #define S32_NVIC_IP_PRI405_MASK 0xFFu 1948 #define S32_NVIC_IP_PRI406_SHIFT 0u 1949 #define S32_NVIC_IP_PRI406_WIDTH 8u 1950 #define S32_NVIC_IP_PRI406(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI406_SHIFT))&S32_NVIC_IP_PRI406_MASK) 1951 #define S32_NVIC_IP_PRI406_MASK 0xFFu 1952 #define S32_NVIC_IP_PRI406_SHIFT 0u 1953 #define S32_NVIC_IP_PRI407_WIDTH 8u 1954 #define S32_NVIC_IP_PRI407(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI407_SHIFT))&S32_NVIC_IP_PRI407_MASK) 1955 #define S32_NVIC_IP_PRI407_MASK 0xFFu 1956 #define S32_NVIC_IP_PRI407_SHIFT 0u 1957 #define S32_NVIC_IP_PRI407_WIDTH 8u 1958 #define S32_NVIC_IP_PRI408(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI408_SHIFT))&S32_NVIC_IP_PRI408_MASK) 1959 #define S32_NVIC_IP_PRI408_MASK 0xFFu 1960 #define S32_NVIC_IP_PRI408_SHIFT 0u 1961 #define S32_NVIC_IP_PRI408_WIDTH 8u 1962 #define S32_NVIC_IP_PRI408(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI408_SHIFT))&S32_NVIC_IP_PRI408_MASK) 1963 #define S32_NVIC_IP_PRI409_MASK 0xFFu 1964 #define S32_NVIC_IP_PRI409_SHIFT 0u 1965 #define S32_NVIC_IP_PRI409_WIDTH 8u 1966 #define S32_NVIC_IP_PRI409(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI409_SHIFT))&S32_NVIC_IP_PRI409_MASK) 1967 #define S32_NVIC_IP_PRI409_MASK 0xFFu 1968 #define S32_NVIC_IP_PRI410_SHIFT 0u 1969 #define S32_NVIC_IP_PRI410_WIDTH 8u 1970 #define S32_NVIC_IP_PRI410(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI410_SHIFT))&S32_NVIC_IP_PRI410_MASK) 1971 #define S32_NVIC_IP_PRI410_MASK 0xFFu 1972 #define S32_NVIC_IP_PRI410_SHIFT 0u 1973 #define S32_NVIC_IP_PRI411_WIDTH 8u 1974 #define S32_NVIC_IP_PRI411(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI411_SHIFT))&S32_NVIC_IP_PRI411_MASK) 1975 #define S32_NVIC_IP_PRI411_MASK 0xFFu 1976 #define S32_NVIC_IP_PRI411_SHIFT 0u 1977 #define S32_NVIC_IP_PRI411_WIDTH 8u 1978 #define S32_NVIC_IP_PRI412(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI412_SHIFT))&S32_NVIC_IP_PRI412_MASK) 1979 #define S32_NVIC_IP_PRI412_MASK 0xFFu 1980 #define S32_NVIC_IP_PRI412_SHIFT 0u 1981 #define S32_NVIC_IP_PRI412_WIDTH 8u 1982 #define S32_NVIC_IP_PRI412(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI412_SHIFT))&S32_NVIC_IP_PRI412_MASK) 1983 #define S32_NVIC_IP_PRI413_MASK 0xFFu 1984 #define S32_NVIC_IP_PRI413_SHIFT 0u 1985 #define S32_NVIC_IP_PRI413_WIDTH 8u 1986 #define S32_NVIC_IP_PRI413(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI413_SHIFT))&S32_NVIC_IP_PRI413_MASK) 1987 #define S32_NVIC_IP_PRI413_MASK 0xFFu 1988 #define S32_NVIC_IP_PRI414_SHIFT 0u 1989 #define S32_NVIC_IP_PRI414_WIDTH 8u 1990 #define S32_NVIC_IP_PRI414(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI414_SHIFT))&S32_NVIC_IP_PRI414_MASK) 1991 #define S32_NVIC_IP_PRI414_MASK 0xFFu 1992 #define S32_NVIC_IP_PRI414_SHIFT 0u 1993 #define S32_NVIC_IP_PRI415_WIDTH 8u 1994 #define S32_NVIC_IP_PRI415(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI415_SHIFT))&S32_NVIC_IP_PRI415_MASK) 1995 #define S32_NVIC_IP_PRI415_MASK 0xFFu 1996 #define S32_NVIC_IP_PRI415_SHIFT 0u 1997 #define S32_NVIC_IP_PRI415_WIDTH 8u 1998 #define S32_NVIC_IP_PRI416(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI416_SHIFT))&S32_NVIC_IP_PRI416_MASK) 1999 #define S32_NVIC_IP_PRI416_MASK 0xFFu 2000 #define S32_NVIC_IP_PRI416_SHIFT 0u 2001 #define S32_NVIC_IP_PRI416_WIDTH 8u 2002 #define S32_NVIC_IP_PRI416(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI416_SHIFT))&S32_NVIC_IP_PRI416_MASK) 2003 #define S32_NVIC_IP_PRI417_MASK 0xFFu 2004 #define S32_NVIC_IP_PRI417_SHIFT 0u 2005 #define S32_NVIC_IP_PRI417_WIDTH 8u 2006 #define S32_NVIC_IP_PRI417(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI417_SHIFT))&S32_NVIC_IP_PRI417_MASK) 2007 #define S32_NVIC_IP_PRI417_MASK 0xFFu 2008 #define S32_NVIC_IP_PRI418_SHIFT 0u 2009 #define S32_NVIC_IP_PRI418_WIDTH 8u 2010 #define S32_NVIC_IP_PRI418(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI418_SHIFT))&S32_NVIC_IP_PRI418_MASK) 2011 #define S32_NVIC_IP_PRI418_MASK 0xFFu 2012 #define S32_NVIC_IP_PRI418_SHIFT 0u 2013 #define S32_NVIC_IP_PRI419_WIDTH 8u 2014 #define S32_NVIC_IP_PRI419(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI419_SHIFT))&S32_NVIC_IP_PRI419_MASK) 2015 #define S32_NVIC_IP_PRI419_MASK 0xFFu 2016 #define S32_NVIC_IP_PRI419_SHIFT 0u 2017 #define S32_NVIC_IP_PRI419_WIDTH 8u 2018 #define S32_NVIC_IP_PRI420(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI420_SHIFT))&S32_NVIC_IP_PRI420_MASK) 2019 #define S32_NVIC_IP_PRI420_MASK 0xFFu 2020 #define S32_NVIC_IP_PRI420_SHIFT 0u 2021 #define S32_NVIC_IP_PRI420_WIDTH 8u 2022 #define S32_NVIC_IP_PRI420(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI420_SHIFT))&S32_NVIC_IP_PRI420_MASK) 2023 #define S32_NVIC_IP_PRI421_MASK 0xFFu 2024 #define S32_NVIC_IP_PRI421_SHIFT 0u 2025 #define S32_NVIC_IP_PRI421_WIDTH 8u 2026 #define S32_NVIC_IP_PRI421(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI421_SHIFT))&S32_NVIC_IP_PRI421_MASK) 2027 #define S32_NVIC_IP_PRI421_MASK 0xFFu 2028 #define S32_NVIC_IP_PRI422_SHIFT 0u 2029 #define S32_NVIC_IP_PRI422_WIDTH 8u 2030 #define S32_NVIC_IP_PRI422(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI422_SHIFT))&S32_NVIC_IP_PRI422_MASK) 2031 #define S32_NVIC_IP_PRI422_MASK 0xFFu 2032 #define S32_NVIC_IP_PRI422_SHIFT 0u 2033 #define S32_NVIC_IP_PRI423_WIDTH 8u 2034 #define S32_NVIC_IP_PRI423(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI423_SHIFT))&S32_NVIC_IP_PRI423_MASK) 2035 #define S32_NVIC_IP_PRI423_MASK 0xFFu 2036 #define S32_NVIC_IP_PRI423_SHIFT 0u 2037 #define S32_NVIC_IP_PRI423_WIDTH 8u 2038 #define S32_NVIC_IP_PRI424(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI424_SHIFT))&S32_NVIC_IP_PRI424_MASK) 2039 #define S32_NVIC_IP_PRI424_MASK 0xFFu 2040 #define S32_NVIC_IP_PRI424_SHIFT 0u 2041 #define S32_NVIC_IP_PRI424_WIDTH 8u 2042 #define S32_NVIC_IP_PRI424(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI424_SHIFT))&S32_NVIC_IP_PRI424_MASK) 2043 #define S32_NVIC_IP_PRI425_MASK 0xFFu 2044 #define S32_NVIC_IP_PRI425_SHIFT 0u 2045 #define S32_NVIC_IP_PRI425_WIDTH 8u 2046 #define S32_NVIC_IP_PRI425(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI425_SHIFT))&S32_NVIC_IP_PRI425_MASK) 2047 #define S32_NVIC_IP_PRI425_MASK 0xFFu 2048 #define S32_NVIC_IP_PRI426_SHIFT 0u 2049 #define S32_NVIC_IP_PRI426_WIDTH 8u 2050 #define S32_NVIC_IP_PRI426(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI426_SHIFT))&S32_NVIC_IP_PRI426_MASK) 2051 #define S32_NVIC_IP_PRI426_MASK 0xFFu 2052 #define S32_NVIC_IP_PRI426_SHIFT 0u 2053 #define S32_NVIC_IP_PRI427_WIDTH 8u 2054 #define S32_NVIC_IP_PRI427(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI427_SHIFT))&S32_NVIC_IP_PRI427_MASK) 2055 #define S32_NVIC_IP_PRI427_MASK 0xFFu 2056 #define S32_NVIC_IP_PRI427_SHIFT 0u 2057 #define S32_NVIC_IP_PRI427_WIDTH 8u 2058 #define S32_NVIC_IP_PRI428(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI428_SHIFT))&S32_NVIC_IP_PRI428_MASK) 2059 #define S32_NVIC_IP_PRI428_MASK 0xFFu 2060 #define S32_NVIC_IP_PRI428_SHIFT 0u 2061 #define S32_NVIC_IP_PRI428_WIDTH 8u 2062 #define S32_NVIC_IP_PRI428(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI428_SHIFT))&S32_NVIC_IP_PRI428_MASK) 2063 #define S32_NVIC_IP_PRI429_MASK 0xFFu 2064 #define S32_NVIC_IP_PRI429_SHIFT 0u 2065 #define S32_NVIC_IP_PRI429_WIDTH 8u 2066 #define S32_NVIC_IP_PRI429(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI429_SHIFT))&S32_NVIC_IP_PRI429_MASK) 2067 #define S32_NVIC_IP_PRI429_MASK 0xFFu 2068 #define S32_NVIC_IP_PRI430_SHIFT 0u 2069 #define S32_NVIC_IP_PRI430_WIDTH 8u 2070 #define S32_NVIC_IP_PRI430(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI430_SHIFT))&S32_NVIC_IP_PRI430_MASK) 2071 #define S32_NVIC_IP_PRI430_MASK 0xFFu 2072 #define S32_NVIC_IP_PRI430_SHIFT 0u 2073 #define S32_NVIC_IP_PRI431_WIDTH 8u 2074 #define S32_NVIC_IP_PRI431(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI431_SHIFT))&S32_NVIC_IP_PRI431_MASK) 2075 #define S32_NVIC_IP_PRI431_MASK 0xFFu 2076 #define S32_NVIC_IP_PRI431_SHIFT 0u 2077 #define S32_NVIC_IP_PRI431_WIDTH 8u 2078 #define S32_NVIC_IP_PRI432(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI432_SHIFT))&S32_NVIC_IP_PRI432_MASK) 2079 #define S32_NVIC_IP_PRI432_MASK 0xFFu 2080 #define S32_NVIC_IP_PRI432_SHIFT 0u 2081 #define S32_NVIC_IP_PRI432_WIDTH 8u 2082 #define S32_NVIC_IP_PRI432(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI432_SHIFT))&S32_NVIC_IP_PRI432_MASK) 2083 #define S32_NVIC_IP_PRI433_MASK 0xFFu 2084 #define S32_NVIC_IP_PRI433_SHIFT 0u 2085 #define S32_NVIC_IP_PRI433_WIDTH 8u 2086 #define S32_NVIC_IP_PRI433(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI433_SHIFT))&S32_NVIC_IP_PRI433_MASK) 2087 #define S32_NVIC_IP_PRI433_MASK 0xFFu 2088 #define S32_NVIC_IP_PRI434_SHIFT 0u 2089 #define S32_NVIC_IP_PRI434_WIDTH 8u 2090 #define S32_NVIC_IP_PRI434(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI434_SHIFT))&S32_NVIC_IP_PRI434_MASK) 2091 #define S32_NVIC_IP_PRI434_MASK 0xFFu 2092 #define S32_NVIC_IP_PRI434_SHIFT 0u 2093 #define S32_NVIC_IP_PRI435_WIDTH 8u 2094 #define S32_NVIC_IP_PRI435(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI435_SHIFT))&S32_NVIC_IP_PRI435_MASK) 2095 #define S32_NVIC_IP_PRI435_MASK 0xFFu 2096 #define S32_NVIC_IP_PRI435_SHIFT 0u 2097 #define S32_NVIC_IP_PRI435_WIDTH 8u 2098 #define S32_NVIC_IP_PRI436(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI436_SHIFT))&S32_NVIC_IP_PRI436_MASK) 2099 #define S32_NVIC_IP_PRI436_MASK 0xFFu 2100 #define S32_NVIC_IP_PRI436_SHIFT 0u 2101 #define S32_NVIC_IP_PRI436_WIDTH 8u 2102 #define S32_NVIC_IP_PRI436(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI436_SHIFT))&S32_NVIC_IP_PRI436_MASK) 2103 #define S32_NVIC_IP_PRI437_MASK 0xFFu 2104 #define S32_NVIC_IP_PRI437_SHIFT 0u 2105 #define S32_NVIC_IP_PRI437_WIDTH 8u 2106 #define S32_NVIC_IP_PRI437(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI437_SHIFT))&S32_NVIC_IP_PRI437_MASK) 2107 #define S32_NVIC_IP_PRI437_MASK 0xFFu 2108 #define S32_NVIC_IP_PRI438_SHIFT 0u 2109 #define S32_NVIC_IP_PRI438_WIDTH 8u 2110 #define S32_NVIC_IP_PRI438(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI438_SHIFT))&S32_NVIC_IP_PRI438_MASK) 2111 #define S32_NVIC_IP_PRI438_MASK 0xFFu 2112 #define S32_NVIC_IP_PRI438_SHIFT 0u 2113 #define S32_NVIC_IP_PRI439_WIDTH 8u 2114 #define S32_NVIC_IP_PRI439(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI439_SHIFT))&S32_NVIC_IP_PRI439_MASK) 2115 #define S32_NVIC_IP_PRI439_MASK 0xFFu 2116 #define S32_NVIC_IP_PRI439_SHIFT 0u 2117 #define S32_NVIC_IP_PRI439_WIDTH 8u 2118 #define S32_NVIC_IP_PRI440(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI440_SHIFT))&S32_NVIC_IP_PRI440_MASK) 2119 #define S32_NVIC_IP_PRI440_MASK 0xFFu 2120 #define S32_NVIC_IP_PRI440_SHIFT 0u 2121 #define S32_NVIC_IP_PRI440_WIDTH 8u 2122 #define S32_NVIC_IP_PRI440(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI440_SHIFT))&S32_NVIC_IP_PRI440_MASK) 2123 #define S32_NVIC_IP_PRI441_MASK 0xFFu 2124 #define S32_NVIC_IP_PRI441_SHIFT 0u 2125 #define S32_NVIC_IP_PRI441_WIDTH 8u 2126 #define S32_NVIC_IP_PRI441(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI441_SHIFT))&S32_NVIC_IP_PRI441_MASK) 2127 #define S32_NVIC_IP_PRI441_MASK 0xFFu 2128 #define S32_NVIC_IP_PRI442_SHIFT 0u 2129 #define S32_NVIC_IP_PRI442_WIDTH 8u 2130 #define S32_NVIC_IP_PRI442(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI442_SHIFT))&S32_NVIC_IP_PRI442_MASK) 2131 #define S32_NVIC_IP_PRI442_MASK 0xFFu 2132 #define S32_NVIC_IP_PRI442_SHIFT 0u 2133 #define S32_NVIC_IP_PRI443_WIDTH 8u 2134 #define S32_NVIC_IP_PRI443(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI443_SHIFT))&S32_NVIC_IP_PRI443_MASK) 2135 #define S32_NVIC_IP_PRI443_MASK 0xFFu 2136 #define S32_NVIC_IP_PRI443_SHIFT 0u 2137 #define S32_NVIC_IP_PRI443_WIDTH 8u 2138 #define S32_NVIC_IP_PRI444(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI444_SHIFT))&S32_NVIC_IP_PRI444_MASK) 2139 #define S32_NVIC_IP_PRI444_MASK 0xFFu 2140 #define S32_NVIC_IP_PRI444_SHIFT 0u 2141 #define S32_NVIC_IP_PRI444_WIDTH 8u 2142 #define S32_NVIC_IP_PRI444(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI444_SHIFT))&S32_NVIC_IP_PRI444_MASK) 2143 #define S32_NVIC_IP_PRI445_MASK 0xFFu 2144 #define S32_NVIC_IP_PRI445_SHIFT 0u 2145 #define S32_NVIC_IP_PRI445_WIDTH 8u 2146 #define S32_NVIC_IP_PRI445(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI445_SHIFT))&S32_NVIC_IP_PRI445_MASK) 2147 #define S32_NVIC_IP_PRI445_MASK 0xFFu 2148 #define S32_NVIC_IP_PRI446_SHIFT 0u 2149 #define S32_NVIC_IP_PRI446_WIDTH 8u 2150 #define S32_NVIC_IP_PRI446(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI446_SHIFT))&S32_NVIC_IP_PRI446_MASK) 2151 #define S32_NVIC_IP_PRI446_MASK 0xFFu 2152 #define S32_NVIC_IP_PRI446_SHIFT 0u 2153 #define S32_NVIC_IP_PRI447_WIDTH 8u 2154 #define S32_NVIC_IP_PRI447(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI447_SHIFT))&S32_NVIC_IP_PRI447_MASK) 2155 #define S32_NVIC_IP_PRI447_MASK 0xFFu 2156 #define S32_NVIC_IP_PRI447_SHIFT 0u 2157 #define S32_NVIC_IP_PRI447_WIDTH 8u 2158 #define S32_NVIC_IP_PRI448(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI448_SHIFT))&S32_NVIC_IP_PRI448_MASK) 2159 #define S32_NVIC_IP_PRI448_MASK 0xFFu 2160 #define S32_NVIC_IP_PRI448_SHIFT 0u 2161 #define S32_NVIC_IP_PRI448_WIDTH 8u 2162 #define S32_NVIC_IP_PRI448(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI448_SHIFT))&S32_NVIC_IP_PRI448_MASK) 2163 #define S32_NVIC_IP_PRI449_MASK 0xFFu 2164 #define S32_NVIC_IP_PRI449_SHIFT 0u 2165 #define S32_NVIC_IP_PRI449_WIDTH 8u 2166 #define S32_NVIC_IP_PRI449(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI449_SHIFT))&S32_NVIC_IP_PRI449_MASK) 2167 #define S32_NVIC_IP_PRI449_MASK 0xFFu 2168 #define S32_NVIC_IP_PRI450_SHIFT 0u 2169 #define S32_NVIC_IP_PRI450_WIDTH 8u 2170 #define S32_NVIC_IP_PRI450(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI450_SHIFT))&S32_NVIC_IP_PRI450_MASK) 2171 #define S32_NVIC_IP_PRI450_MASK 0xFFu 2172 #define S32_NVIC_IP_PRI450_SHIFT 0u 2173 #define S32_NVIC_IP_PRI451_WIDTH 8u 2174 #define S32_NVIC_IP_PRI451(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI451_SHIFT))&S32_NVIC_IP_PRI451_MASK) 2175 #define S32_NVIC_IP_PRI451_MASK 0xFFu 2176 #define S32_NVIC_IP_PRI451_SHIFT 0u 2177 #define S32_NVIC_IP_PRI451_WIDTH 8u 2178 #define S32_NVIC_IP_PRI452(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI452_SHIFT))&S32_NVIC_IP_PRI452_MASK) 2179 #define S32_NVIC_IP_PRI452_MASK 0xFFu 2180 #define S32_NVIC_IP_PRI452_SHIFT 0u 2181 #define S32_NVIC_IP_PRI452_WIDTH 8u 2182 #define S32_NVIC_IP_PRI452(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI452_SHIFT))&S32_NVIC_IP_PRI452_MASK) 2183 #define S32_NVIC_IP_PRI453_MASK 0xFFu 2184 #define S32_NVIC_IP_PRI453_SHIFT 0u 2185 #define S32_NVIC_IP_PRI453_WIDTH 8u 2186 #define S32_NVIC_IP_PRI453(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI453_SHIFT))&S32_NVIC_IP_PRI453_MASK) 2187 #define S32_NVIC_IP_PRI453_MASK 0xFFu 2188 #define S32_NVIC_IP_PRI454_SHIFT 0u 2189 #define S32_NVIC_IP_PRI454_WIDTH 8u 2190 #define S32_NVIC_IP_PRI454(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI454_SHIFT))&S32_NVIC_IP_PRI454_MASK) 2191 #define S32_NVIC_IP_PRI454_MASK 0xFFu 2192 #define S32_NVIC_IP_PRI454_SHIFT 0u 2193 #define S32_NVIC_IP_PRI455_WIDTH 8u 2194 #define S32_NVIC_IP_PRI455(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI455_SHIFT))&S32_NVIC_IP_PRI455_MASK) 2195 #define S32_NVIC_IP_PRI455_MASK 0xFFu 2196 #define S32_NVIC_IP_PRI455_SHIFT 0u 2197 #define S32_NVIC_IP_PRI455_WIDTH 8u 2198 #define S32_NVIC_IP_PRI456(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI456_SHIFT))&S32_NVIC_IP_PRI456_MASK) 2199 #define S32_NVIC_IP_PRI456_MASK 0xFFu 2200 #define S32_NVIC_IP_PRI456_SHIFT 0u 2201 #define S32_NVIC_IP_PRI456_WIDTH 8u 2202 #define S32_NVIC_IP_PRI456(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI456_SHIFT))&S32_NVIC_IP_PRI456_MASK) 2203 #define S32_NVIC_IP_PRI457_MASK 0xFFu 2204 #define S32_NVIC_IP_PRI457_SHIFT 0u 2205 #define S32_NVIC_IP_PRI457_WIDTH 8u 2206 #define S32_NVIC_IP_PRI457(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI457_SHIFT))&S32_NVIC_IP_PRI457_MASK) 2207 #define S32_NVIC_IP_PRI457_MASK 0xFFu 2208 #define S32_NVIC_IP_PRI458_SHIFT 0u 2209 #define S32_NVIC_IP_PRI458_WIDTH 8u 2210 #define S32_NVIC_IP_PRI458(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI458_SHIFT))&S32_NVIC_IP_PRI458_MASK) 2211 #define S32_NVIC_IP_PRI458_MASK 0xFFu 2212 #define S32_NVIC_IP_PRI458_SHIFT 0u 2213 #define S32_NVIC_IP_PRI459_WIDTH 8u 2214 #define S32_NVIC_IP_PRI459(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI459_SHIFT))&S32_NVIC_IP_PRI459_MASK) 2215 #define S32_NVIC_IP_PRI459_MASK 0xFFu 2216 #define S32_NVIC_IP_PRI459_SHIFT 0u 2217 #define S32_NVIC_IP_PRI459_WIDTH 8u 2218 #define S32_NVIC_IP_PRI460(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI460_SHIFT))&S32_NVIC_IP_PRI460_MASK) 2219 #define S32_NVIC_IP_PRI460_MASK 0xFFu 2220 #define S32_NVIC_IP_PRI460_SHIFT 0u 2221 #define S32_NVIC_IP_PRI460_WIDTH 8u 2222 #define S32_NVIC_IP_PRI460(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI460_SHIFT))&S32_NVIC_IP_PRI460_MASK) 2223 #define S32_NVIC_IP_PRI461_MASK 0xFFu 2224 #define S32_NVIC_IP_PRI461_SHIFT 0u 2225 #define S32_NVIC_IP_PRI461_WIDTH 8u 2226 #define S32_NVIC_IP_PRI461(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI461_SHIFT))&S32_NVIC_IP_PRI461_MASK) 2227 #define S32_NVIC_IP_PRI461_MASK 0xFFu 2228 #define S32_NVIC_IP_PRI462_SHIFT 0u 2229 #define S32_NVIC_IP_PRI462_WIDTH 8u 2230 #define S32_NVIC_IP_PRI462(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI462_SHIFT))&S32_NVIC_IP_PRI462_MASK) 2231 #define S32_NVIC_IP_PRI462_MASK 0xFFu 2232 #define S32_NVIC_IP_PRI462_SHIFT 0u 2233 #define S32_NVIC_IP_PRI463_WIDTH 8u 2234 #define S32_NVIC_IP_PRI463(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI463_SHIFT))&S32_NVIC_IP_PRI463_MASK) 2235 #define S32_NVIC_IP_PRI463_MASK 0xFFu 2236 #define S32_NVIC_IP_PRI463_SHIFT 0u 2237 #define S32_NVIC_IP_PRI463_WIDTH 8u 2238 #define S32_NVIC_IP_PRI464(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI464_SHIFT))&S32_NVIC_IP_PRI464_MASK) 2239 #define S32_NVIC_IP_PRI464_MASK 0xFFu 2240 #define S32_NVIC_IP_PRI464_SHIFT 0u 2241 #define S32_NVIC_IP_PRI464_WIDTH 8u 2242 #define S32_NVIC_IP_PRI464(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI464_SHIFT))&S32_NVIC_IP_PRI464_MASK) 2243 #define S32_NVIC_IP_PRI465_MASK 0xFFu 2244 #define S32_NVIC_IP_PRI465_SHIFT 0u 2245 #define S32_NVIC_IP_PRI465_WIDTH 8u 2246 #define S32_NVIC_IP_PRI465(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI465_SHIFT))&S32_NVIC_IP_PRI465_MASK) 2247 #define S32_NVIC_IP_PRI465_MASK 0xFFu 2248 #define S32_NVIC_IP_PRI466_SHIFT 0u 2249 #define S32_NVIC_IP_PRI466_WIDTH 8u 2250 #define S32_NVIC_IP_PRI466(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI466_SHIFT))&S32_NVIC_IP_PRI466_MASK) 2251 #define S32_NVIC_IP_PRI466_MASK 0xFFu 2252 #define S32_NVIC_IP_PRI466_SHIFT 0u 2253 #define S32_NVIC_IP_PRI467_WIDTH 8u 2254 #define S32_NVIC_IP_PRI467(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI467_SHIFT))&S32_NVIC_IP_PRI467_MASK) 2255 #define S32_NVIC_IP_PRI467_MASK 0xFFu 2256 #define S32_NVIC_IP_PRI467_SHIFT 0u 2257 #define S32_NVIC_IP_PRI467_WIDTH 8u 2258 #define S32_NVIC_IP_PRI468(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI468_SHIFT))&S32_NVIC_IP_PRI468_MASK) 2259 #define S32_NVIC_IP_PRI468_MASK 0xFFu 2260 #define S32_NVIC_IP_PRI468_SHIFT 0u 2261 #define S32_NVIC_IP_PRI468_WIDTH 8u 2262 #define S32_NVIC_IP_PRI468(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI468_SHIFT))&S32_NVIC_IP_PRI468_MASK) 2263 #define S32_NVIC_IP_PRI469_MASK 0xFFu 2264 #define S32_NVIC_IP_PRI469_SHIFT 0u 2265 #define S32_NVIC_IP_PRI469_WIDTH 8u 2266 #define S32_NVIC_IP_PRI469(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI469_SHIFT))&S32_NVIC_IP_PRI469_MASK) 2267 #define S32_NVIC_IP_PRI469_MASK 0xFFu 2268 #define S32_NVIC_IP_PRI470_SHIFT 0u 2269 #define S32_NVIC_IP_PRI470_WIDTH 8u 2270 #define S32_NVIC_IP_PRI470(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI470_SHIFT))&S32_NVIC_IP_PRI470_MASK) 2271 #define S32_NVIC_IP_PRI470_MASK 0xFFu 2272 #define S32_NVIC_IP_PRI470_SHIFT 0u 2273 #define S32_NVIC_IP_PRI471_WIDTH 8u 2274 #define S32_NVIC_IP_PRI471(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI471_SHIFT))&S32_NVIC_IP_PRI471_MASK) 2275 #define S32_NVIC_IP_PRI471_MASK 0xFFu 2276 #define S32_NVIC_IP_PRI471_SHIFT 0u 2277 #define S32_NVIC_IP_PRI471_WIDTH 8u 2278 #define S32_NVIC_IP_PRI472(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI472_SHIFT))&S32_NVIC_IP_PRI472_MASK) 2279 #define S32_NVIC_IP_PRI472_MASK 0xFFu 2280 #define S32_NVIC_IP_PRI472_SHIFT 0u 2281 #define S32_NVIC_IP_PRI472_WIDTH 8u 2282 #define S32_NVIC_IP_PRI472(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI472_SHIFT))&S32_NVIC_IP_PRI472_MASK) 2283 #define S32_NVIC_IP_PRI473_MASK 0xFFu 2284 #define S32_NVIC_IP_PRI473_SHIFT 0u 2285 #define S32_NVIC_IP_PRI473_WIDTH 8u 2286 #define S32_NVIC_IP_PRI473(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI473_SHIFT))&S32_NVIC_IP_PRI473_MASK) 2287 #define S32_NVIC_IP_PRI473_MASK 0xFFu 2288 #define S32_NVIC_IP_PRI474_SHIFT 0u 2289 #define S32_NVIC_IP_PRI474_WIDTH 8u 2290 #define S32_NVIC_IP_PRI474(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI474_SHIFT))&S32_NVIC_IP_PRI474_MASK) 2291 #define S32_NVIC_IP_PRI474_MASK 0xFFu 2292 #define S32_NVIC_IP_PRI474_SHIFT 0u 2293 #define S32_NVIC_IP_PRI475_WIDTH 8u 2294 #define S32_NVIC_IP_PRI475(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI475_SHIFT))&S32_NVIC_IP_PRI475_MASK) 2295 #define S32_NVIC_IP_PRI475_MASK 0xFFu 2296 #define S32_NVIC_IP_PRI475_SHIFT 0u 2297 #define S32_NVIC_IP_PRI475_WIDTH 8u 2298 #define S32_NVIC_IP_PRI476(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI476_SHIFT))&S32_NVIC_IP_PRI476_MASK) 2299 #define S32_NVIC_IP_PRI476_MASK 0xFFu 2300 #define S32_NVIC_IP_PRI476_SHIFT 0u 2301 #define S32_NVIC_IP_PRI476_WIDTH 8u 2302 #define S32_NVIC_IP_PRI476(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI476_SHIFT))&S32_NVIC_IP_PRI476_MASK) 2303 #define S32_NVIC_IP_PRI477_MASK 0xFFu 2304 #define S32_NVIC_IP_PRI477_SHIFT 0u 2305 #define S32_NVIC_IP_PRI477_WIDTH 8u 2306 #define S32_NVIC_IP_PRI477(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI477_SHIFT))&S32_NVIC_IP_PRI477_MASK) 2307 #define S32_NVIC_IP_PRI477_MASK 0xFFu 2308 #define S32_NVIC_IP_PRI478_SHIFT 0u 2309 #define S32_NVIC_IP_PRI478_WIDTH 8u 2310 #define S32_NVIC_IP_PRI478(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI478_SHIFT))&S32_NVIC_IP_PRI478_MASK) 2311 #define S32_NVIC_IP_PRI478_MASK 0xFFu 2312 #define S32_NVIC_IP_PRI478_SHIFT 0u 2313 #define S32_NVIC_IP_PRI479_WIDTH 8u 2314 #define S32_NVIC_IP_PRI479(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI479_SHIFT))&S32_NVIC_IP_PRI479_MASK) 2315 #define S32_NVIC_IP_PRI479_MASK 0xFFu 2316 #define S32_NVIC_IP_PRI479_SHIFT 0u 2317 #define S32_NVIC_IP_PRI479_WIDTH 8u 2318 /* STIR Bit Fields */ 2319 #define S32_NVIC_STIR_INTID_MASK 0x1FFu 2320 #define S32_NVIC_STIR_INTID_SHIFT 0u 2321 #define S32_NVIC_STIR_INTID_WIDTH 9u 2322 #define S32_NVIC_STIR_INTID(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_STIR_INTID_SHIFT))&S32_NVIC_STIR_INTID_MASK) 2323 2324 /*! 2325 * @} 2326 */ /* end of group S32_NVIC_Register_Masks */ 2327 2328 /*! 2329 * @} 2330 */ /* end of group S32_NVIC_Peripheral_Access_Layer */ 2331 2332 #endif /* #if !defined(S32Z2_NVIC_H_) */ 2333
