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Searched refs:RX_THD (Results 1 – 25 of 31) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/smartcard/
Dfsl_smartcard_emvsim.c214 rx_thd = (base->RX_THD & ~EMVSIM_RX_THD_RDT_MASK); in smartcard_emvsim_StartReceiveData()
216 base->RX_THD = rx_thd; in smartcard_emvsim_StartReceiveData()
220 base->RX_THD = ((base->RX_THD & ~EMVSIM_RX_THD_RDT_MASK) | context->rxFifoThreshold); in smartcard_emvsim_StartReceiveData()
277 base->RX_THD = EMVSIM_RX_THD_RDT(1); in smartcard_emvsim_SetTransferType()
310 … base->RX_THD = (EMVSIM_RX_THD_RNCK_THD(SMARTCARD_EMV_RX_NACK_THRESHOLD) | EMVSIM_RX_THD_RDT(1)); in smartcard_emvsim_SetTransferType()
368 … base->RX_THD = (EMVSIM_RX_THD_RNCK_THD(SMARTCARD_EMV_RX_NACK_THRESHOLD) | EMVSIM_RX_THD_RDT(1)); in smartcard_emvsim_SetTransferType()
438 base->RX_THD = 1u; in SMARTCARD_EMVSIM_Init()
902 rx_thd = (base->RX_THD & ~EMVSIM_RX_THD_RDT_MASK); in SMARTCARD_EMVSIM_IRQHandler()
904 base->RX_THD = rx_thd; in SMARTCARD_EMVSIM_IRQHandler()
1101 base->RX_THD = ((base->RX_THD & ~EMVSIM_RX_THD_RDT_MASK) | 1u); in SMARTCARD_EMVSIM_Control()
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A31A/
DK32L2A31A.h4178 __IO uint32_t RX_THD; /**< Receiver Threshold Register, offset: 0x18 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A41A/
DK32L2A41A.h4178 __IO uint32_t RX_THD; /**< Receiver Threshold Register, offset: 0x18 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L3A60/
DK32L3A60_cm4.h5282 __IO uint32_t RX_THD; /**< Receiver Threshold Register, offset: 0x18 */ member
DK32L3A60_cm0plus.h4335 __IO uint32_t RX_THD; /**< Receiver Threshold Register, offset: 0x18 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MK80F25615/
DMK80F25615.h8745 __IO uint32_t RX_THD; /**< Receiver Threshold Register, offset: 0x18 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MK82F25615/
DMK82F25615.h8739 __IO uint32_t RX_THD; /**< Receiver Threshold Register, offset: 0x18 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm4.h30689 __IO uint32_t RX_THD; /**< Receiver Threshold Register, offset: 0x18 */ member
DMIMXRT1165_cm7.h30691 __IO uint32_t RX_THD; /**< Receiver Threshold Register, offset: 0x18 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h31003 __IO uint32_t RX_THD; /**< Receiver Threshold Register, offset: 0x18 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QM6/
DMIMX8QM6_ca53.h22909 __IO uint32_t RX_THD; /**< Receiver Threshold Register, offset: 0x18 */ member
DMIMX8QM6_dsp.h23409 __IO uint32_t RX_THD; /**< Receiver Threshold Register, offset: 0x18 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core1.h15800 __IO uint32_t RX_THD; /**< Receiver Threshold, offset: 0x18 */ member
DMCXN546_cm33_core0.h15800 __IO uint32_t RX_THD; /**< Receiver Threshold, offset: 0x18 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h15846 __IO uint32_t RX_THD; /**< Receiver Threshold, offset: 0x18 */ member
DMCXN946_cm33_core1.h15846 __IO uint32_t RX_THD; /**< Receiver Threshold, offset: 0x18 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h31001 __IO uint32_t RX_THD; /**< Receiver Threshold Register, offset: 0x18 */ member
DMIMXRT1175_cm7.h31003 __IO uint32_t RX_THD; /**< Receiver Threshold Register, offset: 0x18 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core1.h15800 __IO uint32_t RX_THD; /**< Receiver Threshold, offset: 0x18 */ member
DMCXN547_cm33_core0.h15800 __IO uint32_t RX_THD; /**< Receiver Threshold, offset: 0x18 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h15846 __IO uint32_t RX_THD; /**< Receiver Threshold, offset: 0x18 */ member
DMCXN947_cm33_core0.h15846 __IO uint32_t RX_THD; /**< Receiver Threshold, offset: 0x18 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm7.h33005 __IO uint32_t RX_THD; /**< Receiver Threshold Register, offset: 0x18 */ member
DMIMXRT1173_cm4.h33003 __IO uint32_t RX_THD; /**< Receiver Threshold Register, offset: 0x18 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm7.h32696 __IO uint32_t RX_THD; /**< Receiver Threshold Register, offset: 0x18 */ member

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