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Searched refs:RX_STATUS (Results 1 – 25 of 32) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/smartcard/
Dfsl_smartcard_emvsim.c87 base->RX_STATUS = EMVSIM_RX_STATUS_RX_DATA_MASK; in smartcard_emvsim_CompleteSendData()
116 while (((base->RX_STATUS & EMVSIM_RX_STATUS_RX_CNT_MASK) != 0u) && ((context->xSize) > 0u)) in smartcard_emvsim_CompleteReceiveData()
282 base->RX_STATUS = 0xFFFFFFFFu; in smartcard_emvsim_SetTransferType()
735 if ((base->RX_STATUS & EMVSIM_RX_STATUS_PEF_MASK) != 0u) in SMARTCARD_EMVSIM_IRQHandler()
739 base->RX_STATUS = EMVSIM_RX_STATUS_PEF_MASK; in SMARTCARD_EMVSIM_IRQHandler()
754 if ((base->RX_STATUS & EMVSIM_RX_STATUS_RTE_MASK) != 0u) in SMARTCARD_EMVSIM_IRQHandler()
758 base->RX_STATUS = EMVSIM_RX_STATUS_RTE_MASK; in SMARTCARD_EMVSIM_IRQHandler()
766 ((base->RX_STATUS & EMVSIM_RX_STATUS_CWT_ERR_MASK) != 0u)) in SMARTCARD_EMVSIM_IRQHandler()
772 base->RX_STATUS = EMVSIM_RX_STATUS_CWT_ERR_MASK; in SMARTCARD_EMVSIM_IRQHandler()
792 ((base->RX_STATUS & EMVSIM_RX_STATUS_BWT_ERR_MASK) != 0u)) in SMARTCARD_EMVSIM_IRQHandler()
[all …]
Dfsl_smartcard_phy_emvsim.c157 emvsimBase->RX_STATUS = 0xFFFFFFFFu; in SMARTCARD_PHY_Activate()
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A41A/
DK32L2A41A.h4180 __IO uint32_t RX_STATUS; /**< Receive Status Register, offset: 0x20 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A31A/
DK32L2A31A.h4180 __IO uint32_t RX_STATUS; /**< Receive Status Register, offset: 0x20 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L3A60/
DK32L3A60_cm4.h5284 __IO uint32_t RX_STATUS; /**< Receive Status Register, offset: 0x20 */ member
DK32L3A60_cm0plus.h4337 __IO uint32_t RX_STATUS; /**< Receive Status Register, offset: 0x20 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MK80F25615/
DMK80F25615.h8747 __IO uint32_t RX_STATUS; /**< Receive Status Register, offset: 0x20 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MK82F25615/
DMK82F25615.h8741 __IO uint32_t RX_STATUS; /**< Receive Status Register, offset: 0x20 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h15802 __IO uint32_t RX_STATUS; /**< Receive Status, offset: 0x20 */ member
DMCXN546_cm33_core1.h15802 __IO uint32_t RX_STATUS; /**< Receive Status, offset: 0x20 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h15802 __IO uint32_t RX_STATUS; /**< Receive Status, offset: 0x20 */ member
DMCXN547_cm33_core1.h15802 __IO uint32_t RX_STATUS; /**< Receive Status, offset: 0x20 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h31003 __IO uint32_t RX_STATUS; /**< Receive Status Register, offset: 0x20 */ member
DMIMXRT1175_cm7.h31005 __IO uint32_t RX_STATUS; /**< Receive Status Register, offset: 0x20 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h30693 __IO uint32_t RX_STATUS; /**< Receive Status Register, offset: 0x20 */ member
DMIMXRT1165_cm4.h30691 __IO uint32_t RX_STATUS; /**< Receive Status Register, offset: 0x20 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h31005 __IO uint32_t RX_STATUS; /**< Receive Status Register, offset: 0x20 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h15848 __IO uint32_t RX_STATUS; /**< Receive Status, offset: 0x20 */ member
DMCXN947_cm33_core0.h15848 __IO uint32_t RX_STATUS; /**< Receive Status, offset: 0x20 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h15848 __IO uint32_t RX_STATUS; /**< Receive Status, offset: 0x20 */ member
DMCXN946_cm33_core1.h15848 __IO uint32_t RX_STATUS; /**< Receive Status, offset: 0x20 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QM6/
DMIMX8QM6_ca53.h22911 __IO uint32_t RX_STATUS; /**< Receive Status Register, offset: 0x20 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm4.h32696 __IO uint32_t RX_STATUS; /**< Receive Status Register, offset: 0x20 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm4.h33005 __IO uint32_t RX_STATUS; /**< Receive Status Register, offset: 0x20 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/
DMIMXRT1172.h33010 __IO uint32_t RX_STATUS; /**< Receive Status Register, offset: 0x20 */ member

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