Home
last modified time | relevance | path

Searched refs:RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_MASK (Results 1 – 16 of 16) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/drivers/
Dfsl_reset.h74 …kRSTCTL_SourceItrcSw = RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_MASK, /*!< ITRC_SW (Intrusion and Tamper R…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/drivers/
Dfsl_reset.h74 …kRSTCTL_SourceItrcSw = RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_MASK, /*!< ITRC_SW (Intrusion and Tamper R…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/drivers/
Dfsl_reset.h74 …kRSTCTL_SourceItrcSw = RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_MASK, /*!< ITRC_SW (Intrusion and Tamper R…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h41412 #define RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_MASK (0x8U) macro
41418 …(uint32_t)(x)) << RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_SHIFT)) & RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_MASK)
DMIMXRT735S_cm33_core1.h41472 #define RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_MASK (0x8U) macro
41478 …(uint32_t)(x)) << RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_SHIFT)) & RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_MASK)
DMIMXRT735S_ezhv.h59723 #define RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_MASK (0x8U) macro
59729 …(uint32_t)(x)) << RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_SHIFT)) & RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_MASK)
DMIMXRT735S_cm33_core0.h59287 #define RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_MASK (0x8U) macro
59293 …(uint32_t)(x)) << RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_SHIFT)) & RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core1.h44695 #define RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_MASK (0x8U) macro
44701 …(uint32_t)(x)) << RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_SHIFT)) & RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_MASK)
DMIMXRT758S_hifi1.h44633 #define RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_MASK (0x8U) macro
44639 …(uint32_t)(x)) << RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_SHIFT)) & RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_MASK)
DMIMXRT758S_cm33_core0.h62512 #define RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_MASK (0x8U) macro
62518 …(uint32_t)(x)) << RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_SHIFT)) & RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_MASK)
DMIMXRT758S_ezhv.h62868 #define RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_MASK (0x8U) macro
62874 …(uint32_t)(x)) << RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_SHIFT)) & RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi1.h44633 #define RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_MASK (0x8U) macro
44639 …(uint32_t)(x)) << RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_SHIFT)) & RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_MASK)
DMIMXRT798S_cm33_core1.h44695 #define RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_MASK (0x8U) macro
44701 …(uint32_t)(x)) << RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_SHIFT)) & RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_MASK)
DMIMXRT798S_hifi4.h62427 #define RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_MASK (0x8U) macro
62433 …(uint32_t)(x)) << RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_SHIFT)) & RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_MASK)
DMIMXRT798S_cm33_core0.h62512 #define RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_MASK (0x8U) macro
62518 …(uint32_t)(x)) << RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_SHIFT)) & RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_MASK)
DMIMXRT798S_ezhv.h62892 #define RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_MASK (0x8U) macro
62898 …(uint32_t)(x)) << RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_SHIFT)) & RSTCTL3_SYSRSTSTAT_ITRC_SW_RESET_MASK)