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Searched refs:RSTCTL2 (Results 1 – 16 of 16) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/drivers/
Dfsl_reset.c95 RSTCTL2->PRSTCTL0_SET = bitMask; in RESET_SetPeripheralReset()
96 while (0u == (RSTCTL2->PRSTCTL0 & bitMask)) in RESET_SetPeripheralReset()
196 RSTCTL2->PRSTCTL0_CLR = bitMask; in RESET_ClearPeripheralReset()
197 while (bitMask == (RSTCTL2->PRSTCTL0 & bitMask)) in RESET_ClearPeripheralReset()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/drivers/
Dfsl_reset.c95 RSTCTL2->PRSTCTL0_SET = bitMask; in RESET_SetPeripheralReset()
96 while (0u == (RSTCTL2->PRSTCTL0 & bitMask)) in RESET_SetPeripheralReset()
196 RSTCTL2->PRSTCTL0_CLR = bitMask; in RESET_ClearPeripheralReset()
197 while (bitMask == (RSTCTL2->PRSTCTL0 & bitMask)) in RESET_ClearPeripheralReset()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/drivers/
Dfsl_reset.c95 RSTCTL2->PRSTCTL0_SET = bitMask; in RESET_SetPeripheralReset()
96 while (0u == (RSTCTL2->PRSTCTL0 & bitMask)) in RESET_SetPeripheralReset()
196 RSTCTL2->PRSTCTL0_CLR = bitMask; in RESET_ClearPeripheralReset()
197 while (bitMask == (RSTCTL2->PRSTCTL0 & bitMask)) in RESET_ClearPeripheralReset()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h41325 #define RSTCTL2 ((RSTCTL2_Type *)RSTCTL2_BASE) macro
41331 #define RSTCTL2_BASE_PTRS { RSTCTL2 }
41340 #define RSTCTL2 ((RSTCTL2_Type *)RSTCTL2_BASE) macro
41344 #define RSTCTL2_BASE_PTRS { RSTCTL2 }
DMIMXRT735S_cm33_core1.h41385 #define RSTCTL2 ((RSTCTL2_Type *)RSTCTL2_BASE) macro
41391 #define RSTCTL2_BASE_PTRS { RSTCTL2 }
41400 #define RSTCTL2 ((RSTCTL2_Type *)RSTCTL2_BASE) macro
41404 #define RSTCTL2_BASE_PTRS { RSTCTL2 }
DMIMXRT735S_cm33_core0.h59200 #define RSTCTL2 ((RSTCTL2_Type *)RSTCTL2_BASE) macro
59206 #define RSTCTL2_BASE_PTRS { RSTCTL2 }
59215 #define RSTCTL2 ((RSTCTL2_Type *)RSTCTL2_BASE) macro
59219 #define RSTCTL2_BASE_PTRS { RSTCTL2 }
DMIMXRT735S_ezhv.h59652 #define RSTCTL2 ((RSTCTL2_Type *)RSTCTL2_BASE) macro
59656 #define RSTCTL2_BASE_PTRS { RSTCTL2 }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core1.h44608 #define RSTCTL2 ((RSTCTL2_Type *)RSTCTL2_BASE) macro
44614 #define RSTCTL2_BASE_PTRS { RSTCTL2 }
44623 #define RSTCTL2 ((RSTCTL2_Type *)RSTCTL2_BASE) macro
44627 #define RSTCTL2_BASE_PTRS { RSTCTL2 }
DMIMXRT758S_hifi1.h44546 #define RSTCTL2 ((RSTCTL2_Type *)RSTCTL2_BASE) macro
44552 #define RSTCTL2_BASE_PTRS { RSTCTL2 }
44561 #define RSTCTL2 ((RSTCTL2_Type *)RSTCTL2_BASE) macro
44565 #define RSTCTL2_BASE_PTRS { RSTCTL2 }
DMIMXRT758S_cm33_core0.h62425 #define RSTCTL2 ((RSTCTL2_Type *)RSTCTL2_BASE) macro
62431 #define RSTCTL2_BASE_PTRS { RSTCTL2 }
62440 #define RSTCTL2 ((RSTCTL2_Type *)RSTCTL2_BASE) macro
62444 #define RSTCTL2_BASE_PTRS { RSTCTL2 }
DMIMXRT758S_ezhv.h62797 #define RSTCTL2 ((RSTCTL2_Type *)RSTCTL2_BASE) macro
62801 #define RSTCTL2_BASE_PTRS { RSTCTL2 }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi1.h44546 #define RSTCTL2 ((RSTCTL2_Type *)RSTCTL2_BASE) macro
44552 #define RSTCTL2_BASE_PTRS { RSTCTL2 }
44561 #define RSTCTL2 ((RSTCTL2_Type *)RSTCTL2_BASE) macro
44565 #define RSTCTL2_BASE_PTRS { RSTCTL2 }
DMIMXRT798S_cm33_core1.h44608 #define RSTCTL2 ((RSTCTL2_Type *)RSTCTL2_BASE) macro
44614 #define RSTCTL2_BASE_PTRS { RSTCTL2 }
44623 #define RSTCTL2 ((RSTCTL2_Type *)RSTCTL2_BASE) macro
44627 #define RSTCTL2_BASE_PTRS { RSTCTL2 }
DMIMXRT798S_hifi4.h62340 #define RSTCTL2 ((RSTCTL2_Type *)RSTCTL2_BASE) macro
62346 #define RSTCTL2_BASE_PTRS { RSTCTL2 }
62355 #define RSTCTL2 ((RSTCTL2_Type *)RSTCTL2_BASE) macro
62359 #define RSTCTL2_BASE_PTRS { RSTCTL2 }
DMIMXRT798S_cm33_core0.h62425 #define RSTCTL2 ((RSTCTL2_Type *)RSTCTL2_BASE) macro
62431 #define RSTCTL2_BASE_PTRS { RSTCTL2 }
62440 #define RSTCTL2 ((RSTCTL2_Type *)RSTCTL2_BASE) macro
62444 #define RSTCTL2_BASE_PTRS { RSTCTL2 }
DMIMXRT798S_ezhv.h62821 #define RSTCTL2 ((RSTCTL2_Type *)RSTCTL2_BASE) macro
62825 #define RSTCTL2_BASE_PTRS { RSTCTL2 }