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Searched refs:REG_3P0 (Results 1 – 25 of 25) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/drivers/pmu/
Dfsl_pmu.h286 base->REG_3P0 = (base->REG_3P0 & ~PMU_REG_3P0_OUTPUT_TRG_MASK) | PMU_REG_3P0_OUTPUT_TRG(value); in PMU_3P0SetRegulatorOutputVoltage()
300 base->REG_3P0 = (base->REG_3P0 & ~PMU_REG_3P0_VBUS_SEL_MASK) | PMU_REG_3P0_VBUS_SEL(option); in PMU_3P0SetVBusVoltageSource()
316 base->REG_3P0 = (base->REG_3P0 & ~PMU_REG_3P0_BO_OFFSET_MASK) | PMU_REG_3P0_BO_OFFSET(value); in PMU_3P0SetBrownoutOffsetVoltage()
329 base->REG_3P0 |= PMU_REG_3P0_ENABLE_ILIMIT_MASK; in PMU_3P0EnableCurrentLimit()
333 base->REG_3P0 &= ~PMU_REG_3P0_ENABLE_ILIMIT_MASK; in PMU_3P0EnableCurrentLimit()
347 base->REG_3P0 |= PMU_REG_3P0_ENABLE_BO_MASK; in PMU_3P0EnableBrownout()
351 base->REG_3P0 &= ~PMU_REG_3P0_ENABLE_BO_MASK; in PMU_3P0EnableBrownout()
365 base->REG_3P0 |= PMU_REG_3P0_ENABLE_LINREG_MASK; in PMU_3P0EnableOutput()
369 base->REG_3P0 &= ~PMU_REG_3P0_ENABLE_LINREG_MASK; in PMU_3P0EnableOutput()
Dfsl_pmu.c35 if (PMU_REG_3P0_OK_VDD3P0_MASK == (PMU_REG_3P0_OK_VDD3P0_MASK & base->REG_3P0)) in PMU_GetStatusFlags()
39 if (PMU_REG_3P0_BO_VDD3P0_MASK == (PMU_REG_3P0_BO_VDD3P0_MASK & base->REG_3P0)) in PMU_GetStatusFlags()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/drivers/
Dfsl_clock.c503 PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | in CLOCK_EnableUsbhs0Clock()
530 PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | in CLOCK_EnableUsbhs1Clock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/drivers/
Dfsl_clock.c495 PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | in CLOCK_EnableUsbhs0Clock()
522 PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | in CLOCK_EnableUsbhs1Clock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/drivers/
Dfsl_clock.c499 PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | in CLOCK_EnableUsbhs0Clock()
526 PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | in CLOCK_EnableUsbhs1Clock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/drivers/
Dfsl_clock.c503 PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | in CLOCK_EnableUsbhs0Clock()
530 PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | in CLOCK_EnableUsbhs1Clock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/drivers/
Dfsl_clock.c503 PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | in CLOCK_EnableUsbhs0Clock()
530 PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | in CLOCK_EnableUsbhs1Clock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/drivers/
Dfsl_clock.c490 PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | in CLOCK_EnableUsbhs0Clock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/drivers/
Dfsl_clock.c490 PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | in CLOCK_EnableUsbhs0Clock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/drivers/
Dfsl_clock.c523 PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | in CLOCK_EnableUsbhs0Clock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/drivers/
Dfsl_clock.c484 PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | in CLOCK_EnableUsbhs0Clock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/drivers/
Dfsl_clock.c497 PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | in CLOCK_EnableUsbhs0Clock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/drivers/
Dfsl_clock.c497 PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | in CLOCK_EnableUsbhs0Clock()
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h28577 …__IO uint32_t REG_3P0; /**< Regulator 3P0 Register, offset: 0x120 … member
28610 #define PMU_REG_3P0_REG(base) ((base)->REG_3P0)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h22446 __IO uint32_t REG_3P0; /**< Regulator 3P0 Register, offset: 0x120 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h25056 __IO uint32_t REG_3P0; /**< Regulator 3P0 Register, offset: 0x120 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h29099 __IO uint32_t REG_3P0; /**< Regulator 3P0 Register, offset: 0x120 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h29120 __IO uint32_t REG_3P0; /**< Regulator 3P0 Register, offset: 0x120 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h30171 __IO uint32_t REG_3P0; /**< Regulator 3P0 Register, offset: 0x120 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h31568 __IO uint32_t REG_3P0; /**< Regulator 3P0 Register, offset: 0x120 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h32878 __IO uint32_t REG_3P0; /**< Regulator 3P0 Register, offset: 0x120 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h33419 __IO uint32_t REG_3P0; /**< Regulator 3P0 Register, offset: 0x120 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h32310 __IO uint32_t REG_3P0; /**< Regulator 3P0 Register, offset: 0x120 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h34952 __IO uint32_t REG_3P0; /**< Regulator 3P0 Register, offset: 0x120 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h34945 __IO uint32_t REG_3P0; /**< Regulator 3P0 Register, offset: 0x120 */ member