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Searched refs:PUF_HW_RUC0_ACCESS_LEVEL_MASK (Results 1 – 18 of 18) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S36/
DLPC55S36.h36222 #define PUF_HW_RUC0_ACCESS_LEVEL_MASK (0xF0000000U) macro
36225 … (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_ACCESS_LEVEL_SHIFT)) & PUF_HW_RUC0_ACCESS_LEVEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h46053 #define PUF_HW_RUC0_ACCESS_LEVEL_MASK (0xF0000000U) macro
46056 … (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_ACCESS_LEVEL_SHIFT)) & PUF_HW_RUC0_ACCESS_LEVEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h46023 #define PUF_HW_RUC0_ACCESS_LEVEL_MASK (0xF0000000U) macro
46026 … (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_ACCESS_LEVEL_SHIFT)) & PUF_HW_RUC0_ACCESS_LEVEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h57652 #define PUF_HW_RUC0_ACCESS_LEVEL_MASK (0xF0000000U) macro
57655 … (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_ACCESS_LEVEL_SHIFT)) & PUF_HW_RUC0_ACCESS_LEVEL_MASK)
DMCXN546_cm33_core1.h57652 #define PUF_HW_RUC0_ACCESS_LEVEL_MASK (0xF0000000U) macro
57655 … (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_ACCESS_LEVEL_SHIFT)) & PUF_HW_RUC0_ACCESS_LEVEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h57652 #define PUF_HW_RUC0_ACCESS_LEVEL_MASK (0xF0000000U) macro
57655 … (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_ACCESS_LEVEL_SHIFT)) & PUF_HW_RUC0_ACCESS_LEVEL_MASK)
DMCXN547_cm33_core1.h57652 #define PUF_HW_RUC0_ACCESS_LEVEL_MASK (0xF0000000U) macro
57655 … (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_ACCESS_LEVEL_SHIFT)) & PUF_HW_RUC0_ACCESS_LEVEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi4.h59937 #define PUF_HW_RUC0_ACCESS_LEVEL_MASK (0xF0000000U) macro
59940 … (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_ACCESS_LEVEL_SHIFT)) & PUF_HW_RUC0_ACCESS_LEVEL_MASK)
DMIMXRT798S_cm33_core0.h60022 #define PUF_HW_RUC0_ACCESS_LEVEL_MASK (0xF0000000U) macro
60025 … (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_ACCESS_LEVEL_SHIFT)) & PUF_HW_RUC0_ACCESS_LEVEL_MASK)
DMIMXRT798S_ezhv.h59904 #define PUF_HW_RUC0_ACCESS_LEVEL_MASK (0xF0000000U) macro
59907 … (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_ACCESS_LEVEL_SHIFT)) & PUF_HW_RUC0_ACCESS_LEVEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_ezhv.h56735 #define PUF_HW_RUC0_ACCESS_LEVEL_MASK (0xF0000000U) macro
56738 … (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_ACCESS_LEVEL_SHIFT)) & PUF_HW_RUC0_ACCESS_LEVEL_MASK)
DMIMXRT735S_cm33_core0.h56797 #define PUF_HW_RUC0_ACCESS_LEVEL_MASK (0xF0000000U) macro
56800 … (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_ACCESS_LEVEL_SHIFT)) & PUF_HW_RUC0_ACCESS_LEVEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core0.h60022 #define PUF_HW_RUC0_ACCESS_LEVEL_MASK (0xF0000000U) macro
60025 … (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_ACCESS_LEVEL_SHIFT)) & PUF_HW_RUC0_ACCESS_LEVEL_MASK)
DMIMXRT758S_ezhv.h59880 #define PUF_HW_RUC0_ACCESS_LEVEL_MASK (0xF0000000U) macro
59883 … (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_ACCESS_LEVEL_SHIFT)) & PUF_HW_RUC0_ACCESS_LEVEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h58387 #define PUF_HW_RUC0_ACCESS_LEVEL_MASK (0xF0000000U) macro
58390 … (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_ACCESS_LEVEL_SHIFT)) & PUF_HW_RUC0_ACCESS_LEVEL_MASK)
DMCXN947_cm33_core0.h58387 #define PUF_HW_RUC0_ACCESS_LEVEL_MASK (0xF0000000U) macro
58390 … (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_ACCESS_LEVEL_SHIFT)) & PUF_HW_RUC0_ACCESS_LEVEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h58387 #define PUF_HW_RUC0_ACCESS_LEVEL_MASK (0xF0000000U) macro
58390 … (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_ACCESS_LEVEL_SHIFT)) & PUF_HW_RUC0_ACCESS_LEVEL_MASK)
DMCXN946_cm33_core1.h58387 #define PUF_HW_RUC0_ACCESS_LEVEL_MASK (0xF0000000U) macro
58390 … (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_ACCESS_LEVEL_SHIFT)) & PUF_HW_RUC0_ACCESS_LEVEL_MASK)