| /hal_nxp-latest/mcux/mcux-sdk/devices/RW612/drivers/ |
| D | fsl_power.c | 934 CLKCTL1->PSCCTL2_SET = rtcClk; in AT_QUICKACCESS_SECTION_CODE()
1285 CLKCTL0->PSCCTL2_SET = CLKCTL0_PSCCTL2_ITRC_MASK; in POWER_DisableGDetVSensors()
1360 CLKCTL0->PSCCTL2_SET = CLKCTL0_PSCCTL2_ITRC_MASK; in POWER_EnableGDetVSensors()
|
| D | fsl_clock.c | 277 CLKCTL0->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
286 CLKCTL1->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/RW610/drivers/ |
| D | fsl_power.c | 934 CLKCTL1->PSCCTL2_SET = rtcClk; in AT_QUICKACCESS_SECTION_CODE()
1285 CLKCTL0->PSCCTL2_SET = CLKCTL0_PSCCTL2_ITRC_MASK; in POWER_DisableGDetVSensors()
1360 CLKCTL0->PSCCTL2_SET = CLKCTL0_PSCCTL2_ITRC_MASK; in POWER_EnableGDetVSensors()
|
| D | fsl_clock.c | 277 CLKCTL0->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
286 CLKCTL1->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/drivers/ |
| D | fsl_clock.h | 898 CLKCTL0->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
907 CLKCTL1->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/drivers/ |
| D | fsl_clock.h | 898 CLKCTL0->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
907 CLKCTL1->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/drivers/ |
| D | fsl_clock.h | 1111 CLKCTL0->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
1120 CLKCTL1->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/drivers/ |
| D | fsl_clock.h | 1111 CLKCTL0->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
1120 CLKCTL1->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/drivers/ |
| D | fsl_clock.h | 1111 CLKCTL0->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
1120 CLKCTL1->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/ |
| D | MIMXRT685S_dsp.h | 1234 __O uint32_t PSCCTL2_SET; /**< clock set register 2, offset: 0x48 */ member
2720 __O uint32_t PSCCTL2_SET; /**< clock set register 2, offset: 0x48 */ member
|
| D | MIMXRT685S_cm33.h | 6945 __O uint32_t PSCCTL2_SET; /**< clock set register 2, offset: 0x48 */ member
8450 __O uint32_t PSCCTL2_SET; /**< clock set register 2, offset: 0x48 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/ |
| D | MIMXRT633S.h | 6945 __O uint32_t PSCCTL2_SET; /**< clock set register 2, offset: 0x48 */ member
8450 __O uint32_t PSCCTL2_SET; /**< clock set register 2, offset: 0x48 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/ |
| D | MIMXRT595S_dsp.h | 1911 __O uint32_t PSCCTL2_SET; /**< Clock Control 2 Set, offset: 0x48 */ member
4110 __IO uint32_t PSCCTL2_SET; /**< Clock Set 2, offset: 0x48 */ member
|
| D | MIMXRT595S_cm33.h | 8149 __O uint32_t PSCCTL2_SET; /**< Clock Control 2 Set, offset: 0x48 */ member
10367 __IO uint32_t PSCCTL2_SET; /**< Clock Set 2, offset: 0x48 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/ |
| D | MIMXRT533S.h | 8145 __O uint32_t PSCCTL2_SET; /**< Clock Control 2 Set, offset: 0x48 */ member
10363 __IO uint32_t PSCCTL2_SET; /**< Clock Set 2, offset: 0x48 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/ |
| D | MIMXRT555S.h | 8148 __O uint32_t PSCCTL2_SET; /**< Clock Control 2 Set, offset: 0x48 */ member
10366 __IO uint32_t PSCCTL2_SET; /**< Clock Set 2, offset: 0x48 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/RW610/ |
| D | RW610.h | 19960 __O uint32_t PSCCTL2_SET; /**< Peripheral clock set 2, offset: 0x48 */ member
21417 __O uint32_t PSCCTL2_SET; /**< Peripheral clock set 2, offset: 0x48 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/RW612/ |
| D | RW612.h | 19960 __O uint32_t PSCCTL2_SET; /**< Peripheral clock set 2, offset: 0x48 */ member
21417 __O uint32_t PSCCTL2_SET; /**< Peripheral clock set 2, offset: 0x48 */ member
|
