| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/drivers/ |
| D | fsl_clock.h | 895 CLKCTL0->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
904 CLKCTL1->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/drivers/ |
| D | fsl_clock.h | 895 CLKCTL0->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
904 CLKCTL1->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/RW612/drivers/ |
| D | fsl_clock.c | 274 CLKCTL0->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
283 CLKCTL1->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
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| D | fsl_power.c | 1284 CLKCTL0->PSCCTL1_SET = CLKCTL0_PSCCTL1_ELS_APB_MASK; in POWER_DisableGDetVSensors()
1359 CLKCTL0->PSCCTL1_SET = CLKCTL0_PSCCTL1_ELS_APB_MASK; in POWER_EnableGDetVSensors()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/RW610/drivers/ |
| D | fsl_clock.c | 274 CLKCTL0->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
283 CLKCTL1->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
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| D | fsl_power.c | 1284 CLKCTL0->PSCCTL1_SET = CLKCTL0_PSCCTL1_ELS_APB_MASK; in POWER_DisableGDetVSensors()
1359 CLKCTL0->PSCCTL1_SET = CLKCTL0_PSCCTL1_ELS_APB_MASK; in POWER_EnableGDetVSensors()
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/sdu/ |
| D | fsl_sdioslv_sdu.c | 78 CLKCTL0->PSCCTL1_SET = CLKCTL0_PSCCTL1_SET_SDIO_SLV(1); in SDIOSLV_Init0()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/drivers/ |
| D | fsl_clock.h | 1108 CLKCTL0->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
1117 CLKCTL1->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/drivers/ |
| D | fsl_clock.h | 1108 CLKCTL0->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
1117 CLKCTL1->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/drivers/ |
| D | fsl_clock.h | 1108 CLKCTL0->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
1117 CLKCTL1->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/ |
| D | MIMXRT685S_dsp.h | 1233 __O uint32_t PSCCTL1_SET; /**< clock set register 1, offset: 0x44 */ member
2719 __O uint32_t PSCCTL1_SET; /**< clock set register 1, offset: 0x44 */ member
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| D | MIMXRT685S_cm33.h | 6944 __O uint32_t PSCCTL1_SET; /**< clock set register 1, offset: 0x44 */ member
8449 __O uint32_t PSCCTL1_SET; /**< clock set register 1, offset: 0x44 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/ |
| D | MIMXRT633S.h | 6944 __O uint32_t PSCCTL1_SET; /**< clock set register 1, offset: 0x44 */ member
8449 __O uint32_t PSCCTL1_SET; /**< clock set register 1, offset: 0x44 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/ |
| D | MIMXRT595S_dsp.h | 1910 __O uint32_t PSCCTL1_SET; /**< Clock Control 1 Set, offset: 0x44 */ member
4109 __IO uint32_t PSCCTL1_SET; /**< Clock Set 1, offset: 0x44 */ member
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| D | MIMXRT595S_cm33.h | 8148 __O uint32_t PSCCTL1_SET; /**< Clock Control 1 Set, offset: 0x44 */ member
10366 __IO uint32_t PSCCTL1_SET; /**< Clock Set 1, offset: 0x44 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/ |
| D | MIMXRT533S.h | 8144 __O uint32_t PSCCTL1_SET; /**< Clock Control 1 Set, offset: 0x44 */ member
10362 __IO uint32_t PSCCTL1_SET; /**< Clock Set 1, offset: 0x44 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/ |
| D | MIMXRT555S.h | 8147 __O uint32_t PSCCTL1_SET; /**< Clock Control 1 Set, offset: 0x44 */ member
10365 __IO uint32_t PSCCTL1_SET; /**< Clock Set 1, offset: 0x44 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/RW610/ |
| D | RW610.h | 19959 __O uint32_t PSCCTL1_SET; /**< Peripheral clock set 1, offset: 0x44 */ member
21416 __O uint32_t PSCCTL1_SET; /**< Peripheral clock set 1, offset: 0x44 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/RW612/ |
| D | RW612.h | 19959 __O uint32_t PSCCTL1_SET; /**< Peripheral clock set 1, offset: 0x44 */ member
21416 __O uint32_t PSCCTL1_SET; /**< Peripheral clock set 1, offset: 0x44 */ member
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