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Searched refs:PSCCTL1_CLR (Results 1 – 16 of 16) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/drivers/
Dfsl_clock.h924 CLKCTL0->PSCCTL1_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
933 CLKCTL1->PSCCTL1_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/drivers/
Dfsl_clock.h924 CLKCTL0->PSCCTL1_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
933 CLKCTL1->PSCCTL1_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/drivers/
Dfsl_clock.c328 CLKCTL0->PSCCTL1_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
337 CLKCTL1->PSCCTL1_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/drivers/
Dfsl_clock.c328 CLKCTL0->PSCCTL1_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
337 CLKCTL1->PSCCTL1_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/drivers/
Dfsl_clock.h1137 CLKCTL0->PSCCTL1_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
1146 CLKCTL1->PSCCTL1_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/drivers/
Dfsl_clock.h1137 CLKCTL0->PSCCTL1_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
1146 CLKCTL1->PSCCTL1_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/drivers/
Dfsl_clock.h1137 CLKCTL0->PSCCTL1_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
1146 CLKCTL1->PSCCTL1_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h1237 __O uint32_t PSCCTL1_CLR; /**< clock clear register 1, offset: 0x74 */ member
2723 __O uint32_t PSCCTL1_CLR; /**< clock clear register 1, offset: 0x74 */ member
DMIMXRT685S_cm33.h6948 __O uint32_t PSCCTL1_CLR; /**< clock clear register 1, offset: 0x74 */ member
8453 __O uint32_t PSCCTL1_CLR; /**< clock clear register 1, offset: 0x74 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h6948 __O uint32_t PSCCTL1_CLR; /**< clock clear register 1, offset: 0x74 */ member
8453 __O uint32_t PSCCTL1_CLR; /**< clock clear register 1, offset: 0x74 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h1914 __O uint32_t PSCCTL1_CLR; /**< Clock Control 1 Clear, offset: 0x74 */ member
4113 __IO uint32_t PSCCTL1_CLR; /**< Clock Clear 1, offset: 0x74 */ member
DMIMXRT595S_cm33.h8152 __O uint32_t PSCCTL1_CLR; /**< Clock Control 1 Clear, offset: 0x74 */ member
10370 __IO uint32_t PSCCTL1_CLR; /**< Clock Clear 1, offset: 0x74 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h8148 __O uint32_t PSCCTL1_CLR; /**< Clock Control 1 Clear, offset: 0x74 */ member
10366 __IO uint32_t PSCCTL1_CLR; /**< Clock Clear 1, offset: 0x74 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h8151 __O uint32_t PSCCTL1_CLR; /**< Clock Control 1 Clear, offset: 0x74 */ member
10369 __IO uint32_t PSCCTL1_CLR; /**< Clock Clear 1, offset: 0x74 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/
DRW610.h19963 __O uint32_t PSCCTL1_CLR; /**< Peripheral clock clear 1, offset: 0x74 */ member
21420 __O uint32_t PSCCTL1_CLR; /**< Peripheral clock clear 1, offset: 0x74 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/
DRW612.h19963 __O uint32_t PSCCTL1_CLR; /**< Peripheral clock clear 1, offset: 0x74 */ member
21420 __O uint32_t PSCCTL1_CLR; /**< Peripheral clock clear 1, offset: 0x74 */ member