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Searched refs:PDRUNCFG0_SET (Results 1 – 25 of 30) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/drivers/
Dfsl_power.c1042 SYSCTL0->PDRUNCFG0_SET = pll_need_pd; in AT_QUICKACCESS_SECTION_CODE()
1116 SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_SET_LPOSC_PD_MASK; in AT_QUICKACCESS_SECTION_CODE()
1125 SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_SET_FFRO_PD_MASK; in AT_QUICKACCESS_SECTION_CODE()
Dfsl_clock.c1370 …SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_SYSPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_SYSPLLANA_PD_MASK; in CLOCK_InitSysPll()
1460 …SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_AUDPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_AUDPLLANA_PD_MASK; in CLOCK_InitAudioPll()
Dfsl_power.h28 #define SYSCTL0_PDRCFGSET_REG(x) (*((volatile uint32_t *)((uint32_t)(&(SYSCTL0->PDRUNCFG0_SET)) + (…
Dfsl_clock.h1451 …SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_SYSPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_SYSPLLANA_PD_MASK; in CLOCK_DeinitSysPll()
1482 …SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_AUDPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_AUDPLLANA_PD_MASK; in CLOCK_DeinitAudioPll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/drivers/
Dfsl_power.c1042 SYSCTL0->PDRUNCFG0_SET = pll_need_pd; in AT_QUICKACCESS_SECTION_CODE()
1116 SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_SET_LPOSC_PD_MASK; in AT_QUICKACCESS_SECTION_CODE()
1125 SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_SET_FFRO_PD_MASK; in AT_QUICKACCESS_SECTION_CODE()
Dfsl_clock.c1370 …SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_SYSPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_SYSPLLANA_PD_MASK; in CLOCK_InitSysPll()
1460 …SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_AUDPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_AUDPLLANA_PD_MASK; in CLOCK_InitAudioPll()
Dfsl_power.h28 #define SYSCTL0_PDRCFGSET_REG(x) (*((volatile uint32_t *)((uint32_t)(&(SYSCTL0->PDRUNCFG0_SET)) + (…
Dfsl_clock.h1451 …SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_SYSPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_SYSPLLANA_PD_MASK; in CLOCK_DeinitSysPll()
1482 …SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_AUDPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_AUDPLLANA_PD_MASK; in CLOCK_DeinitAudioPll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/drivers/
Dfsl_power.c1042 SYSCTL0->PDRUNCFG0_SET = pll_need_pd; in AT_QUICKACCESS_SECTION_CODE()
1116 SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_SET_LPOSC_PD_MASK; in AT_QUICKACCESS_SECTION_CODE()
1125 SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_SET_FFRO_PD_MASK; in AT_QUICKACCESS_SECTION_CODE()
Dfsl_clock.c1370 …SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_SYSPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_SYSPLLANA_PD_MASK; in CLOCK_InitSysPll()
1460 …SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_AUDPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_AUDPLLANA_PD_MASK; in CLOCK_InitAudioPll()
Dfsl_power.h28 #define SYSCTL0_PDRCFGSET_REG(x) (*((volatile uint32_t *)((uint32_t)(&(SYSCTL0->PDRUNCFG0_SET)) + (…
Dfsl_clock.h1451 …SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_SYSPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_SYSPLLANA_PD_MASK; in CLOCK_DeinitSysPll()
1482 …SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_AUDPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_AUDPLLANA_PD_MASK; in CLOCK_DeinitAudioPll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
Dsystem_MIMXRT595S_cm33.c120 …SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_HSPAD_FSPI0_REF_PD_MASK | SYSCTL0_PDRUNCFG0_HSPAD_SDIO0… in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
Dsystem_MIMXRT555S.c119 …SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_HSPAD_FSPI0_REF_PD_MASK | SYSCTL0_PDRUNCFG0_HSPAD_SDIO0… in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
Dsystem_MIMXRT533S.c119 …SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_HSPAD_FSPI0_REF_PD_MASK | SYSCTL0_PDRUNCFG0_HSPAD_SDIO0… in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/drivers/
Dfsl_power.c948 SYSCTL0->PDRUNCFG0_SET = pll_need_pd; in POWER_EnterDeepSleep()
1015 SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_SET_FFRO_PD_MASK; in POWER_EnterDeepSleep()
Dfsl_clock.c1250 …SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_SYSPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_SYSPLLANA_PD_MASK; in CLOCK_InitSysPll()
1338 …SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_AUDPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_AUDPLLANA_PD_MASK; in CLOCK_InitAudioPll()
Dfsl_clock.h1183 …SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_SYSPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_SYSPLLANA_PD_MASK; in CLOCK_DeinitSysPll()
1210 …SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_AUDPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_AUDPLLANA_PD_MASK; in CLOCK_DeinitAudioPll()
Dfsl_power.h27 #define SYSCTL0_PDRCFGSET_REG(x) (*((volatile uint32_t *)((uint32_t)(&(SYSCTL0->PDRUNCFG0_SET)) + (…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/drivers/
Dfsl_power.c948 SYSCTL0->PDRUNCFG0_SET = pll_need_pd; in POWER_EnterDeepSleep()
1015 SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_SET_FFRO_PD_MASK; in POWER_EnterDeepSleep()
Dfsl_clock.c1250 …SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_SYSPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_SYSPLLANA_PD_MASK; in CLOCK_InitSysPll()
1338 …SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_AUDPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_AUDPLLANA_PD_MASK; in CLOCK_InitAudioPll()
Dfsl_clock.h1183 …SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_SYSPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_SYSPLLANA_PD_MASK; in CLOCK_DeinitSysPll()
1210 …SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_AUDPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_AUDPLLANA_PD_MASK; in CLOCK_DeinitAudioPll()
Dfsl_power.h27 #define SYSCTL0_PDRCFGSET_REG(x) (*((volatile uint32_t *)((uint32_t)(&(SYSCTL0->PDRUNCFG0_SET)) + (…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h21087 __O uint32_t PDRUNCFG0_SET; /**< Run configuration 0 set, offset: 0x620 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h30700 __O uint32_t PDRUNCFG0_SET; /**< Run configuration 0 set, offset: 0x620 */ member

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