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Searched refs:PDM_FIFO_CTRL_FIFOWMK_MASK (Results 1 – 25 of 80) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/pdm/
Dfsl_pdm.c317 assert(config->fifoWatermark <= PDM_FIFO_CTRL_FIFOWMK_MASK); in PDM_Init()
521 handle->watermark = (uint8_t)(base->FIFO_CTRL & PDM_FIFO_CTRL_FIFOWMK_MASK); in PDM_TransferCreateHandle()
Dfsl_pdm_sdma.c138 handle->count = (uint8_t)(handle->channelNums * (base->FIFO_CTRL & PDM_FIFO_CTRL_FIFOWMK_MASK)); in PDM_SetChannelConfigSDMA()
Dfsl_pdm_edma.c214 handle->count = (uint8_t)(base->FIFO_CTRL & PDM_FIFO_CTRL_FIFOWMK_MASK); in PDM_TransferSetChannelConfigEDMA()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN5/
DMIMX8MN5_cm7.h42658 #define PDM_FIFO_CTRL_FIFOWMK_MASK (0x7U) macro
42662 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN2/
DMIMX8MN2_cm7.h42656 #define PDM_FIFO_CTRL_FIFOWMK_MASK (0x7U) macro
42660 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN4/
DMIMX8MN4_cm7.h42656 #define PDM_FIFO_CTRL_FIFOWMK_MASK (0x7U) macro
42660 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h33963 #define PDM_FIFO_CTRL_FIFOWMK_MASK (0x7U) macro
33966 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK)
DMIMXRT735S_cm33_core1.h34023 #define PDM_FIFO_CTRL_FIFOWMK_MASK (0x7U) macro
34026 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK)
DMIMXRT735S_ezhv.h49206 #define PDM_FIFO_CTRL_FIFOWMK_MASK (0x7U) macro
49209 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK)
DMIMXRT735S_cm33_core0.h49230 #define PDM_FIFO_CTRL_FIFOWMK_MASK (0x7U) macro
49233 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN3/
DMIMX8MN3_cm7.h42658 #define PDM_FIFO_CTRL_FIFOWMK_MASK (0x7U) macro
42662 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN1/
DMIMX8MN1_cm7.h42658 #define PDM_FIFO_CTRL_FIFOWMK_MASK (0x7U) macro
42662 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN6/
DMIMX8MN6_cm7.h42656 #define PDM_FIFO_CTRL_FIFOWMK_MASK (0x7U) macro
42660 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK)
DMIMX8MN6_ca53.h42670 #define PDM_FIFO_CTRL_FIFOWMK_MASK (0x7U) macro
42674 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core1.h36820 #define PDM_FIFO_CTRL_FIFOWMK_MASK (0x7U) macro
36823 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK)
DMIMXRT758S_hifi1.h36758 #define PDM_FIFO_CTRL_FIFOWMK_MASK (0x7U) macro
36761 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h42959 #define PDM_FIFO_CTRL_FIFOWMK_MASK (0xFU) macro
42962 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h42929 #define PDM_FIFO_CTRL_FIFOWMK_MASK (0xFU) macro
42932 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi1.h36758 #define PDM_FIFO_CTRL_FIFOWMK_MASK (0x7U) macro
36761 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK)
DMIMXRT798S_cm33_core1.h36820 #define PDM_FIFO_CTRL_FIFOWMK_MASK (0x7U) macro
36823 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK)
DMIMXRT798S_hifi4.h51944 #define PDM_FIFO_CTRL_FIFOWMK_MASK (0x7U) macro
51947 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h53786 #define PDM_FIFO_CTRL_FIFOWMK_MASK (0xFU) macro
53789 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h53786 #define PDM_FIFO_CTRL_FIFOWMK_MASK (0xFU) macro
53789 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h59425 #define PDM_FIFO_CTRL_FIFOWMK_MASK (0x7U) macro
59428 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h57999 #define PDM_FIFO_CTRL_FIFOWMK_MASK (0x7U) macro
58002 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK)

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