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Searched refs:PCR (Results 1 – 25 of 134) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/port/
Dfsl_port.h363 uint32_t addr = (uint32_t)&base->PCR[pin]; in PORT_SetPinConfig()
465 base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(mux); in PORT_SetPinMux()
534 base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | PORT_PCR_IRQC(config); in PORT_SetPinInterruptConfig()
550 base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_DSE_MASK) | PORT_PCR_DSE(strength); in PORT_SetPinDriveStrength()
564 base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_DSE1_MASK) | PORT_PCR_DSE1(enable); in PORT_EnablePinDoubleDriveStrength()
580 base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_PV_MASK) | PORT_PCR_PV(value); in PORT_SetPinPullValue()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW22D5/
Dsystem_MKW22D5.c90 …PORTB->PCR[19] = (PORTB->PCR[19] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(0x01u); /* PORTB.19 as GPIO … in ExtClk_Setup_HookUp()
91 … PORTC->PCR[0] = (PORTC->PCR[0] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(0x01u); /* PORTC.0 as GPIO*/ in ExtClk_Setup_HookUp()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW24D5/
Dsystem_MKW24D5.c90 …PORTB->PCR[19] = (PORTB->PCR[19] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(0x01u); /* PORTB.19 as GPIO … in ExtClk_Setup_HookUp()
91 … PORTC->PCR[0] = (PORTC->PCR[0] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(0x01u); /* PORTC.0 as GPIO*/ in ExtClk_Setup_HookUp()
/hal_nxp-latest/mcux/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/
Dfsl_xcvr.c1881 PORTC->PCR[4] = (PORTC->PCR[4] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2); in XCVR_CoexistenceInit()
1882 PORTC->PCR[3] = (PORTC->PCR[3] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2); in XCVR_CoexistenceInit()
1885 PORTC->PCR[1] = (PORTC->PCR[1] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2); in XCVR_CoexistenceInit()
1886 PORTC->PCR[3] = (PORTC->PCR[3] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2); in XCVR_CoexistenceInit()
1913 PORTC->PCR[4] = (PORTC->PCR[4] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2); in XCVR_CoexistenceInit()
1914 PORTC->PCR[1] = (PORTC->PCR[1] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2); in XCVR_CoexistenceInit()
/hal_nxp-latest/mcux/mcux-sdk/drivers/netc/netc_hw/
Dfsl_netc_hw_port.h166 base->PCR = (base->PCR & ~NETC_PORT_PCR_PSPEED_MASK) | NETC_PORT_PCR_PSPEED(pSpeed); in NETC_PortSetSpeed()
326 base->PCR = NETC_PORT_PCR_L2DOSE(config->enL2Dos); in NETC_PortSetIPF()
Dfsl_netc_hw_port.c43 base->PCR = NETC_PORT_PCR_PSPEED(config->pSpeed) | in NETC_PortConfig()
/hal_nxp-latest/mcux/mcux-sdk/drivers/dac14/
Dfsl_dac14.c110 base->PCR = HPDAC_PCR_PTG_NUM(config->periodicTriggerNumber) | in DAC14_Init()
123 base->PCR = HPDAC_PCR_PTG_NUM(config->periodicTriggerNumber) | in DAC14_Init()
/hal_nxp-latest/mcux/mcux-sdk/drivers/dac_1/
Dfsl_dac.c120 base->PCR = in DAC_Init()
126 base->PCR = in DAC_Init()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW40Z4/
Dsystem_MKW40Z4.c104 PORTB->PCR[16] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); in SystemInit()
106 PORTB->PCR[17] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW20Z4/
Dsystem_MKW20Z4.c104 PORTB->PCR[16] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); in SystemInit()
106 PORTB->PCR[17] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW30Z4/
Dsystem_MKW30Z4.c104 PORTB->PCR[16] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); in SystemInit()
106 PORTB->PCR[17] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); in SystemInit()
/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K144_PORT.h76 …__IO uint32_t PCR[PORT_PCR_COUNT]; /**< Pin Control Register n, array offset: 0x0, a… member
DS32K142W_PORT.h76 …__IO uint32_t PCR[PORT_PCR_COUNT]; /**< Pin Control Register n, array offset: 0x0, a… member
DS32K116_PORT.h76 …__IO uint32_t PCR[PORT_PCR_COUNT]; /**< Pin Control Register n, array offset: 0x0, a… member
DS32K118_PORT.h76 …__IO uint32_t PCR[PORT_PCR_COUNT]; /**< Pin Control Register n, array offset: 0x0, a… member
DS32K148_PORT.h76 …__IO uint32_t PCR[PORT_PCR_COUNT]; /**< Pin Control Register n, array offset: 0x0, a… member
DS32K142_PORT.h76 …__IO uint32_t PCR[PORT_PCR_COUNT]; /**< Pin Control Register n, array offset: 0x0, a… member
DS32K146_PORT.h76 …__IO uint32_t PCR[PORT_PCR_COUNT]; /**< Pin Control Register n, array offset: 0x0, a… member
DS32K144W_PORT.h76 …__IO uint32_t PCR[PORT_PCR_COUNT]; /**< Pin Control Register n, array offset: 0x0, a… member
/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_ENETC_PORT.h80 __IO uint32_t PCR; /**< Port configuration register, offset: 0x10 */ member
DS32Z2_SW_PORT2.h80 __IO uint32_t PCR; /**< Port configuration register, offset: 0x10 */ member
DS32Z2_SW_PORT0.h80 __IO uint32_t PCR; /**< Port configuration register, offset: 0x10 */ member
DS32Z2_SW_PORT1.h80 __IO uint32_t PCR; /**< Port configuration register, offset: 0x10 */ member
DS32Z2_RTU_PMC.h76 __IO uint32_t PCR; /**< Program Control Register, offset: 0xC */ member
/hal_nxp-latest/s32/drivers/s32ze/EthSwt_NETC/src/
DNetc_EthSwt_Ip.c1922 Netc_EthSwt_Ip_SW0_PortxBaseAddr[SwitchPortIdx]->PCR &= ~SW_PORT0_PCR_PSPEED_MASK;
1923 … Netc_EthSwt_Ip_SW0_PortxBaseAddr[SwitchPortIdx]->PCR |= SW_PORT0_PCR_PSPEED(shapingPSpeedConfig);
1930 Netc_EthSwt_Ip_SW0_PortxBaseAddr[SwitchPortIdx]->PCR &= ~SW_PORT0_PCR_PSPEED_MASK;
1931 …Netc_EthSwt_Ip_SW0_PortxBaseAddr[SwitchPortIdx]->PCR |= SW_PORT0_PCR_PSPEED(NETC_ETHSWT_IP_SHAPING…
6325 …Netc_EthSwt_Ip_SW0_PortxBaseAddr[SwitchIdxSwitchPort.SwitchPortIdx]->PCR &= ~SW_PORT0_PCR_PSPEED_M…
6326 …Netc_EthSwt_Ip_SW0_PortxBaseAddr[SwitchIdxSwitchPort.SwitchPortIdx]->PCR |= SW_PORT0_PCR_PSPEED(sh…
6350 …Netc_EthSwt_Ip_SW0_PortxBaseAddr[SwitchIdxSwitchPort.SwitchPortIdx]->PCR &= ~SW_PORT0_PCR_PSPEED_M…
6351 …Netc_EthSwt_Ip_SW0_PortxBaseAddr[SwitchIdxSwitchPort.SwitchPortIdx]->PCR |= SW_PORT0_PCR_PSPEED(NE…

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