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Searched refs:PCC1_BASE (Results 1 – 25 of 33) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/K32L3A60/drivers/
Dfsl_clock.h356 kCLOCK_Edma1 = MAKE_PCC_REGADDR(PCC1_BASE, 0x20),
357 kCLOCK_GpioE = MAKE_PCC_REGADDR(PCC1_BASE, 0x3C),
358 kCLOCK_Xrdc0PacB = MAKE_PCC_REGADDR(PCC1_BASE, 0x58),
359 kCLOCK_Xrdc0MrcB = MAKE_PCC_REGADDR(PCC1_BASE, 0x5C),
360 kCLOCK_Sema421 = MAKE_PCC_REGADDR(PCC1_BASE, 0x6C),
361 kCLOCK_Dmamux1 = MAKE_PCC_REGADDR(PCC1_BASE, 0x84),
362 kCLOCK_Intmux0 = MAKE_PCC_REGADDR(PCC1_BASE, 0x88),
363 kCLOCK_MuB = MAKE_PCC_REGADDR(PCC1_BASE, 0x90),
364 kCLOCK_Cau3 = MAKE_PCC_REGADDR(PCC1_BASE, 0xA0),
365 kCLOCK_Trng = MAKE_PCC_REGADDR(PCC1_BASE, 0xA4),
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD7/drivers/
Dfsl_reset.h55 kRESET_Flexspi1 = (uint32_t)(PCC1_BASE + 0x48),
56 kRESET_Tpm0 = (uint32_t)(PCC1_BASE + 0x54),
57 kRESET_Tpm1 = (uint32_t)(PCC1_BASE + 0x58),
58 kRESET_Lpi2c0 = (uint32_t)(PCC1_BASE + 0x60),
59 kRESET_Lpi2c1 = (uint32_t)(PCC1_BASE + 0x64),
60 kRESET_Lpuart0 = (uint32_t)(PCC1_BASE + 0x68),
61 kRESET_Lpuart1 = (uint32_t)(PCC1_BASE + 0x6C),
62 kRESET_Sai0 = (uint32_t)(PCC1_BASE + 0x70),
63 kRESET_Sai1 = (uint32_t)(PCC1_BASE + 0x74),
64 kRESET_Adc1 = (uint32_t)(PCC1_BASE + 0x88),
[all …]
Dfsl_clock.h907 kCLOCK_Tpiu = (uint32_t)(PCC1_BASE + 0xc) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
908 kCLOCK_Swo = (uint32_t)(PCC1_BASE + 0x18) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
909 kCLOCK_Flexspi1 = (uint32_t)(PCC1_BASE + 0x48) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
910 kCLOCK_Lptmr0 = (uint32_t)(PCC1_BASE + 0x4c),
911 kCLOCK_Lptmr1 = (uint32_t)(PCC1_BASE + 0x50),
912 kCLOCK_Tpm0 = (uint32_t)(PCC1_BASE + 0x54) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
913 kCLOCK_Tpm1 = (uint32_t)(PCC1_BASE + 0x58) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
914 kCLOCK_Lpi2c0 = (uint32_t)(PCC1_BASE + 0x60) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
915 kCLOCK_Lpi2c1 = (uint32_t)(PCC1_BASE + 0x64) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
916 kCLOCK_Lpuart0 = (uint32_t)(PCC1_BASE + 0x68) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
[all …]
Dfsl_clock.c229 case (PCC1_BASE & 0x2FFFF000U): in CLOCK_GetPccInstance()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8US5/drivers/
Dfsl_reset.h55 kRESET_Flexspi1 = (uint32_t)(PCC1_BASE + 0x48),
56 kRESET_Tpm0 = (uint32_t)(PCC1_BASE + 0x54),
57 kRESET_Tpm1 = (uint32_t)(PCC1_BASE + 0x58),
58 kRESET_Lpi2c0 = (uint32_t)(PCC1_BASE + 0x60),
59 kRESET_Lpi2c1 = (uint32_t)(PCC1_BASE + 0x64),
60 kRESET_Lpuart0 = (uint32_t)(PCC1_BASE + 0x68),
61 kRESET_Lpuart1 = (uint32_t)(PCC1_BASE + 0x6C),
62 kRESET_Sai0 = (uint32_t)(PCC1_BASE + 0x70),
63 kRESET_Sai1 = (uint32_t)(PCC1_BASE + 0x74),
64 kRESET_Adc1 = (uint32_t)(PCC1_BASE + 0x88),
[all …]
Dfsl_clock.h907 kCLOCK_Tpiu = (uint32_t)(PCC1_BASE + 0xc) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
908 kCLOCK_Swo = (uint32_t)(PCC1_BASE + 0x18) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
909 kCLOCK_Flexspi1 = (uint32_t)(PCC1_BASE + 0x48) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
910 kCLOCK_Lptmr0 = (uint32_t)(PCC1_BASE + 0x4c),
911 kCLOCK_Lptmr1 = (uint32_t)(PCC1_BASE + 0x50),
912 kCLOCK_Tpm0 = (uint32_t)(PCC1_BASE + 0x54) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
913 kCLOCK_Tpm1 = (uint32_t)(PCC1_BASE + 0x58) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
914 kCLOCK_Lpi2c0 = (uint32_t)(PCC1_BASE + 0x60) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
915 kCLOCK_Lpi2c1 = (uint32_t)(PCC1_BASE + 0x64) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
916 kCLOCK_Lpuart0 = (uint32_t)(PCC1_BASE + 0x68) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
[all …]
Dfsl_clock.c229 case (PCC1_BASE & 0x2FFFF000U): in CLOCK_GetPccInstance()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8US3/drivers/
Dfsl_reset.h55 kRESET_Flexspi1 = (uint32_t)(PCC1_BASE + 0x48),
56 kRESET_Tpm0 = (uint32_t)(PCC1_BASE + 0x54),
57 kRESET_Tpm1 = (uint32_t)(PCC1_BASE + 0x58),
58 kRESET_Lpi2c0 = (uint32_t)(PCC1_BASE + 0x60),
59 kRESET_Lpi2c1 = (uint32_t)(PCC1_BASE + 0x64),
60 kRESET_Lpuart0 = (uint32_t)(PCC1_BASE + 0x68),
61 kRESET_Lpuart1 = (uint32_t)(PCC1_BASE + 0x6C),
62 kRESET_Sai0 = (uint32_t)(PCC1_BASE + 0x70),
63 kRESET_Sai1 = (uint32_t)(PCC1_BASE + 0x74),
64 kRESET_Adc1 = (uint32_t)(PCC1_BASE + 0x88),
[all …]
Dfsl_clock.h907 kCLOCK_Tpiu = (uint32_t)(PCC1_BASE + 0xc) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
908 kCLOCK_Swo = (uint32_t)(PCC1_BASE + 0x18) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
909 kCLOCK_Flexspi1 = (uint32_t)(PCC1_BASE + 0x48) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
910 kCLOCK_Lptmr0 = (uint32_t)(PCC1_BASE + 0x4c),
911 kCLOCK_Lptmr1 = (uint32_t)(PCC1_BASE + 0x50),
912 kCLOCK_Tpm0 = (uint32_t)(PCC1_BASE + 0x54) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
913 kCLOCK_Tpm1 = (uint32_t)(PCC1_BASE + 0x58) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
914 kCLOCK_Lpi2c0 = (uint32_t)(PCC1_BASE + 0x60) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
915 kCLOCK_Lpi2c1 = (uint32_t)(PCC1_BASE + 0x64) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
916 kCLOCK_Lpuart0 = (uint32_t)(PCC1_BASE + 0x68) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
[all …]
Dfsl_clock.c229 case (PCC1_BASE & 0x2FFFF000U): in CLOCK_GetPccInstance()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD5/drivers/
Dfsl_reset.h55 kRESET_Flexspi1 = (uint32_t)(PCC1_BASE + 0x48),
56 kRESET_Tpm0 = (uint32_t)(PCC1_BASE + 0x54),
57 kRESET_Tpm1 = (uint32_t)(PCC1_BASE + 0x58),
58 kRESET_Lpi2c0 = (uint32_t)(PCC1_BASE + 0x60),
59 kRESET_Lpi2c1 = (uint32_t)(PCC1_BASE + 0x64),
60 kRESET_Lpuart0 = (uint32_t)(PCC1_BASE + 0x68),
61 kRESET_Lpuart1 = (uint32_t)(PCC1_BASE + 0x6C),
62 kRESET_Sai0 = (uint32_t)(PCC1_BASE + 0x70),
63 kRESET_Sai1 = (uint32_t)(PCC1_BASE + 0x74),
64 kRESET_Adc1 = (uint32_t)(PCC1_BASE + 0x88),
[all …]
Dfsl_clock.h907 kCLOCK_Tpiu = (uint32_t)(PCC1_BASE + 0xc) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
908 kCLOCK_Swo = (uint32_t)(PCC1_BASE + 0x18) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
909 kCLOCK_Flexspi1 = (uint32_t)(PCC1_BASE + 0x48) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
910 kCLOCK_Lptmr0 = (uint32_t)(PCC1_BASE + 0x4c),
911 kCLOCK_Lptmr1 = (uint32_t)(PCC1_BASE + 0x50),
912 kCLOCK_Tpm0 = (uint32_t)(PCC1_BASE + 0x54) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
913 kCLOCK_Tpm1 = (uint32_t)(PCC1_BASE + 0x58) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
914 kCLOCK_Lpi2c0 = (uint32_t)(PCC1_BASE + 0x60) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
915 kCLOCK_Lpi2c1 = (uint32_t)(PCC1_BASE + 0x64) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
916 kCLOCK_Lpuart0 = (uint32_t)(PCC1_BASE + 0x68) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
[all …]
Dfsl_clock.c229 case (PCC1_BASE & 0x2FFFF000U): in CLOCK_GetPccInstance()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD3/drivers/
Dfsl_reset.h55 kRESET_Flexspi1 = (uint32_t)(PCC1_BASE + 0x48),
56 kRESET_Tpm0 = (uint32_t)(PCC1_BASE + 0x54),
57 kRESET_Tpm1 = (uint32_t)(PCC1_BASE + 0x58),
58 kRESET_Lpi2c0 = (uint32_t)(PCC1_BASE + 0x60),
59 kRESET_Lpi2c1 = (uint32_t)(PCC1_BASE + 0x64),
60 kRESET_Lpuart0 = (uint32_t)(PCC1_BASE + 0x68),
61 kRESET_Lpuart1 = (uint32_t)(PCC1_BASE + 0x6C),
62 kRESET_Sai0 = (uint32_t)(PCC1_BASE + 0x70),
63 kRESET_Sai1 = (uint32_t)(PCC1_BASE + 0x74),
64 kRESET_Adc1 = (uint32_t)(PCC1_BASE + 0x88),
[all …]
Dfsl_clock.h907 kCLOCK_Tpiu = (uint32_t)(PCC1_BASE + 0xc) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
908 kCLOCK_Swo = (uint32_t)(PCC1_BASE + 0x18) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
909 kCLOCK_Flexspi1 = (uint32_t)(PCC1_BASE + 0x48) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
910 kCLOCK_Lptmr0 = (uint32_t)(PCC1_BASE + 0x4c),
911 kCLOCK_Lptmr1 = (uint32_t)(PCC1_BASE + 0x50),
912 kCLOCK_Tpm0 = (uint32_t)(PCC1_BASE + 0x54) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
913 kCLOCK_Tpm1 = (uint32_t)(PCC1_BASE + 0x58) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
914 kCLOCK_Lpi2c0 = (uint32_t)(PCC1_BASE + 0x60) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
915 kCLOCK_Lpi2c1 = (uint32_t)(PCC1_BASE + 0x64) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
916 kCLOCK_Lpuart0 = (uint32_t)(PCC1_BASE + 0x68) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
[all …]
Dfsl_clock.c229 case (PCC1_BASE & 0x2FFFF000U): in CLOCK_GetPccInstance()
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A41A/
DK32L2A41A.h12791 #define PCC1_BASE (0x400FA000u) macro
12793 #define PCC1 ((PCC_Type *)PCC1_BASE)
12795 #define PCC_BASE_ADDRS { PCC0_BASE, PCC1_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A31A/
DK32L2A31A.h12791 #define PCC1_BASE (0x400FA000u) macro
12793 #define PCC1 ((PCC_Type *)PCC1_BASE)
12795 #define PCC_BASE_ADDRS { PCC0_BASE, PCC1_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L3A60/
DK32L3A60_cm4.h15960 #define PCC1_BASE (0x41027000u) macro
15962 #define PCC1 ((PCC_Type *)PCC1_BASE)
15964 #define PCC_BASE_ADDRS { PCC0_BASE, PCC1_BASE }
DK32L3A60_cm0plus.h15900 #define PCC1_BASE (0x41027000u) macro
15902 #define PCC1 ((PCC_Type *)PCC1_BASE)
15904 #define PCC_BASE_ADDRS { PCC0_BASE, PCC1_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h24143 #define PCC1_BASE (0x410B2000u) macro
24145 #define PCC1 ((PCC1_Type *)PCC1_BASE)
24147 #define PCC1_BASE_ADDRS { PCC1_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h24144 #define PCC1_BASE (0x410B2000u) macro
24146 #define PCC1 ((PCC1_Type *)PCC1_BASE)
24148 #define PCC1_BASE_ADDRS { PCC1_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD3/
DMIMX8UD3_cm33.h42188 #define PCC1_BASE (0x38091000u) macro
42192 #define PCC1 ((PCC1_Type *)PCC1_BASE)
42196 #define PCC1_BASE_ADDRS { PCC1_BASE }
42205 #define PCC1_BASE (0x28091000u) macro
42207 #define PCC1 ((PCC1_Type *)PCC1_BASE)
42209 #define PCC1_BASE_ADDRS { PCC1_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD7/
DMIMX8UD7_cm33.h42188 #define PCC1_BASE (0x38091000u) macro
42192 #define PCC1 ((PCC1_Type *)PCC1_BASE)
42196 #define PCC1_BASE_ADDRS { PCC1_BASE }
42205 #define PCC1_BASE (0x28091000u) macro
42207 #define PCC1 ((PCC1_Type *)PCC1_BASE)
42209 #define PCC1_BASE_ADDRS { PCC1_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD5/
DMIMX8UD5_cm33.h40580 #define PCC1_BASE (0x38091000u) macro
40584 #define PCC1 ((PCC1_Type *)PCC1_BASE)
40588 #define PCC1_BASE_ADDRS { PCC1_BASE }
40597 #define PCC1_BASE (0x28091000u) macro
40599 #define PCC1 ((PCC1_Type *)PCC1_BASE)
40601 #define PCC1_BASE_ADDRS { PCC1_BASE }

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